Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55793	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

116177

1

T1

865

T2

93

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	99176	1			T1	698		T2	49		T3	11
values[0x0]	34211	1			T1	289		T2	39		T3	5
values[0x1]	38583	1			T1	275		T2	74		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40305	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

131665

1

T1

997

T2

139

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	806	1			T1	2		T2	1		T13	4
valid_sources[0x01]	830	1			T1	7		T2	1		T13	29
valid_sources[0x02]	626	1			T1	6		T16	1		T30	5
valid_sources[0x03]	690	1			T1	2		T2	2		T16	2
valid_sources[0x04]	438	1			T1	3		T16	5		T30	14
valid_sources[0x05]	590	1			T1	3		T37	3		T30	15
valid_sources[0x06]	741	1			T1	4		T4	30		T13	3
valid_sources[0x07]	756	1			T1	4		T2	2		T13	20
valid_sources[0x08]	905	1			T1	6		T2	1		T4	52
valid_sources[0x09]	704	1			T1	5		T2	1		T4	12
valid_sources[0x0a]	585	1			T1	8		T16	2		T30	25
valid_sources[0x0b]	573	1			T1	2		T16	3		T30	7
valid_sources[0x0c]	648	1			T1	5		T2	1		T16	1
valid_sources[0x0d]	743	1			T1	3		T2	1		T27	13
valid_sources[0x0e]	687	1			T1	3		T2	1		T13	46
valid_sources[0x0f]	673	1			T1	9		T4	121		T30	18
valid_sources[0x10]	559	1			T1	3		T16	2		T30	7
valid_sources[0x11]	703	1			T1	10		T30	17		T38	4
valid_sources[0x12]	821	1			T1	4		T15	84		T27	26
valid_sources[0x13]	703	1			T1	1		T4	20		T13	2
valid_sources[0x14]	729	1			T1	3		T2	2		T13	9
valid_sources[0x15]	745	1			T1	6		T2	1		T16	1
valid_sources[0x16]	478	1			T1	6		T16	1		T30	17
valid_sources[0x17]	542	1			T1	7		T2	2		T4	46
valid_sources[0x18]	578	1			T1	9		T13	9		T16	6
valid_sources[0x19]	585	1			T1	4		T16	2		T30	1
valid_sources[0x1a]	680	1			T1	7		T30	4		T38	1
valid_sources[0x1b]	925	1			T1	5		T27	169		T16	2
valid_sources[0x1c]	710	1			T1	1		T2	1		T27	29
valid_sources[0x1d]	744	1			T1	5		T2	2		T10	1
valid_sources[0x1e]	682	1			T1	2		T37	3		T30	11
valid_sources[0x1f]	488	1			T1	8		T5	50		T30	13
valid_sources[0x20]	746	1			T1	3		T2	1		T16	2
valid_sources[0x21]	855	1			T1	5		T14	36		T27	44
valid_sources[0x22]	706	1			T1	5		T2	1		T16	2
valid_sources[0x23]	638	1			T1	10		T2	2		T16	2
valid_sources[0x24]	765	1			T1	10		T2	2		T12	52
valid_sources[0x25]	624	1			T1	3		T5	52		T13	2
valid_sources[0x26]	392	1			T1	3		T2	1		T13	4
valid_sources[0x27]	650	1			T1	5		T14	42		T16	1
valid_sources[0x28]	689	1			T1	4		T13	5		T38	4
valid_sources[0x29]	718	1			T1	1		T16	1		T30	12
valid_sources[0x2a]	684	1			T1	4		T2	1		T13	9
valid_sources[0x2b]	594	1			T1	3		T2	2		T13	18
valid_sources[0x2c]	702	1			T1	6		T5	168		T16	1
valid_sources[0x2d]	669	1			T1	3		T2	3		T27	70
valid_sources[0x2e]	639	1			T1	4		T13	19		T16	2
valid_sources[0x2f]	599	1			T1	7		T2	1		T13	6
valid_sources[0x30]	702	1			T1	4		T16	1		T37	7
valid_sources[0x31]	658	1			T1	6		T13	45		T27	55
valid_sources[0x32]	757	1			T1	4		T2	1		T27	25
valid_sources[0x33]	540	1			T1	4		T4	56		T16	1
valid_sources[0x34]	574	1			T1	7		T16	5		T30	5
valid_sources[0x35]	733	1			T1	7		T16	1		T38	3
valid_sources[0x36]	742	1			T1	9		T16	4		T37	6
valid_sources[0x37]	737	1			T1	6		T13	22		T10	1
valid_sources[0x38]	440	1			T1	3		T2	1		T30	11
valid_sources[0x39]	526	1			T1	9		T13	6		T31	5
valid_sources[0x3a]	736	1			T1	6		T2	1		T4	40
valid_sources[0x3b]	556	1			T1	4		T13	14		T16	4
valid_sources[0x3c]	613	1			T1	2		T2	3		T16	2
valid_sources[0x3d]	775	1			T1	10		T13	6		T27	19
valid_sources[0x3e]	668	1			T1	5		T5	58		T13	2
valid_sources[0x3f]	656	1			T1	7		T4	11		T13	5
valid_sources[0x40]	475	1			T1	7		T16	1		T30	10
valid_sources[0x41]	558	1			T1	7		T2	1		T16	1
valid_sources[0x42]	823	1			T1	3		T2	2		T16	2
valid_sources[0x43]	502	1			T1	4		T13	22		T16	7
valid_sources[0x44]	851	1			T1	9		T13	28		T37	8
valid_sources[0x45]	586	1			T1	4		T13	39		T16	1
valid_sources[0x46]	712	1			T1	3		T16	2		T30	27
valid_sources[0x47]	693	1			T1	10		T5	77		T13	13
valid_sources[0x48]	444	1			T1	5		T4	33		T37	6
valid_sources[0x49]	548	1			T1	6		T37	10		T30	3
valid_sources[0x4a]	731	1			T1	4		T2	3		T4	109
valid_sources[0x4b]	662	1			T1	2		T2	1		T13	12
valid_sources[0x4c]	648	1			T1	5		T16	1		T30	54
valid_sources[0x4d]	630	1			T30	14		T38	1		T31	8
valid_sources[0x4e]	748	1			T1	1		T4	57		T16	2
valid_sources[0x4f]	583	1			T1	8		T2	1		T37	15
valid_sources[0x50]	639	1			T1	3		T4	38		T30	15
valid_sources[0x51]	585	1			T1	2		T30	3		T38	2
valid_sources[0x52]	559	1			T1	4		T16	2		T30	8
valid_sources[0x53]	829	1			T1	2		T2	1		T4	157
valid_sources[0x54]	707	1			T1	6		T13	6		T16	4
valid_sources[0x55]	668	1			T1	9		T2	1		T12	111
valid_sources[0x56]	604	1			T1	5		T4	54		T38	2
valid_sources[0x57]	803	1			T1	2		T2	2		T4	87
valid_sources[0x58]	783	1			T1	1		T13	6		T30	3
valid_sources[0x59]	620	1			T1	7		T2	1		T16	1
valid_sources[0x5a]	667	1			T1	2		T30	8		T31	8
valid_sources[0x5b]	748	1			T1	6		T4	5		T12	50
valid_sources[0x5c]	756	1			T1	9		T13	13		T16	2
valid_sources[0x5d]	721	1			T1	5		T16	1		T38	2
valid_sources[0x5e]	601	1			T1	9		T2	3		T16	3
valid_sources[0x5f]	675	1			T1	2		T4	20		T16	1
valid_sources[0x60]	656	1			T1	2		T2	1		T16	1
valid_sources[0x61]	641	1			T1	5		T2	3		T16	3
valid_sources[0x62]	642	1			T1	8		T5	134		T13	4
valid_sources[0x63]	602	1			T1	2		T2	1		T15	49
valid_sources[0x64]	627	1			T1	1		T5	50		T13	30
valid_sources[0x65]	716	1			T1	6		T2	1		T3	10
valid_sources[0x66]	747	1			T1	4		T27	4		T16	2
valid_sources[0x67]	681	1			T1	7		T15	103		T16	1
valid_sources[0x68]	743	1			T1	3		T2	3		T12	84
valid_sources[0x69]	490	1			T1	2		T2	1		T10	3
valid_sources[0x6a]	620	1			T1	4		T2	2		T16	3
valid_sources[0x6b]	788	1			T1	4		T13	15		T38	3
valid_sources[0x6c]	601	1			T1	4		T10	5		T16	4
valid_sources[0x6d]	570	1			T1	3		T13	5		T16	4
valid_sources[0x6e]	645	1			T1	4		T16	2		T37	8
valid_sources[0x6f]	701	1			T1	1		T9	38		T12	136
valid_sources[0x70]	667	1			T1	2		T2	2		T30	12
valid_sources[0x71]	840	1			T1	4		T13	4		T15	108
valid_sources[0x72]	810	1			T1	5		T4	82		T16	1
valid_sources[0x73]	533	1			T1	1		T30	15		T38	3
valid_sources[0x74]	583	1			T1	1		T16	1		T30	35
valid_sources[0x75]	725	1			T1	6		T2	1		T12	29
valid_sources[0x76]	559	1			T1	7		T2	3		T4	32
valid_sources[0x77]	589	1			T1	4		T30	14		T31	4
valid_sources[0x78]	750	1			T1	3		T2	1		T4	57
valid_sources[0x79]	586	1			T1	4		T4	18		T13	3
valid_sources[0x7a]	764	1			T1	5		T30	12		T38	3
valid_sources[0x7b]	734	1			T1	2		T3	3		T30	19
valid_sources[0x7c]	729	1			T1	4		T2	1		T16	3
valid_sources[0x7d]	668	1			T1	2		T13	52		T16	3
valid_sources[0x7e]	667	1			T1	8		T2	3		T4	9
valid_sources[0x7f]	652	1			T1	6		T37	12		T30	5
valid_sources[0x80]	788	1			T1	4		T4	33		T13	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

56446

1

T1

342

T2

24

T3

5

values[0x0]

all_enables

biggest_size

30129

1

T1

270

T2

36

T3

1

values[0x1]

all_enables

biggest_size

29602

1

T1

253

T2

33

T4

528