Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

74868

1

T1

398

T2

773

T3

16

full_word

117328

1

T1

865

T2

140

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	191916	1			T1	1253		T2	913		T3	22
auto[TlIntgErrCmd]	88	1			T1	5		T4	4		T13	5
auto[TlIntgErrData]	87	1			T1	2		T4	7		T13	2
auto[TlIntgErrBoth]	105	1			T1	3		T4	9		T13	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103481

1

T1

698

T2

293

T3

11

auto[1]

88715

1

T1

565

T2

620

T3

11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	46602	1			T1	351		T2	252		T3	6
auto[TlIntgErrNone]	partial	auto[1]	28011	1			T1	37		T2	521		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	56749	1			T1	342		T2	41		T3	5
auto[TlIntgErrNone]	full_word	auto[1]	60554	1			T1	523		T2	99		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T1	3		T4	3		T13	2
auto[TlIntgErrCmd]	partial	auto[1]	37	1			T1	2		T4	1		T13	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T33	1		T35	1		T32	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T13	1		T33	1		T66	3
auto[TlIntgErrData]	partial	auto[0]	43	1			T1	1		T4	4		T13	1
auto[TlIntgErrData]	partial	auto[1]	36	1			T1	1		T4	2		T13	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T4	1		T63	1		T67	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T35	1		T63	1		T68	2
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T1	1		T4	3		T27	1
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T1	2		T4	6		T13	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T33	1		T34	1		T67	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T27	1		T31	1		T63	1