| | | | | | | |
u_alert_test_fatal_fault_err |
100.00 |
100.00 |
|
|
|
|
|
u_alert_test_recov_operation_err |
100.00 |
100.00 |
|
|
|
|
|
u_cfg_regwen |
100.00 |
100.00 |
|
|
|
|
|
u_cfg_shadowed0_qe |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_cfg_shadowed_en_unsupported_modestrength |
98.66 |
100.00 |
94.64 |
|
|
100.00 |
100.00 |
committed_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
shadow_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
staged_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_cfg_shadowed_entropy_fast_process |
98.66 |
100.00 |
94.64 |
|
|
100.00 |
100.00 |
committed_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
shadow_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
staged_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_cfg_shadowed_entropy_mode |
98.66 |
100.00 |
94.64 |
|
|
100.00 |
100.00 |
committed_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
shadow_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
staged_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_cfg_shadowed_entropy_ready |
98.66 |
100.00 |
94.64 |
|
|
100.00 |
100.00 |
committed_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
shadow_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
staged_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_cfg_shadowed_kmac_en |
98.66 |
100.00 |
94.64 |
|
|
100.00 |
100.00 |
committed_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
shadow_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
staged_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_cfg_shadowed_kstrength |
98.66 |
100.00 |
94.64 |
|
|
100.00 |
100.00 |
committed_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
shadow_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
staged_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_cfg_shadowed_mode |
98.66 |
100.00 |
94.64 |
|
|
100.00 |
100.00 |
committed_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
shadow_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
staged_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_cfg_shadowed_msg_endianness |
98.66 |
100.00 |
94.64 |
|
|
100.00 |
100.00 |
committed_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
shadow_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
staged_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_cfg_shadowed_msg_mask |
98.66 |
100.00 |
94.64 |
|
|
100.00 |
100.00 |
committed_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
shadow_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
staged_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_cfg_shadowed_sideload |
98.66 |
100.00 |
94.64 |
|
|
100.00 |
100.00 |
committed_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
shadow_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
staged_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_cfg_shadowed_state_endianness |
98.66 |
100.00 |
94.64 |
|
|
100.00 |
100.00 |
committed_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
shadow_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
staged_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_chk |
100.00 |
100.00 |
|
100.00 |
|
|
100.00 |
u_chk |
100.00 |
|
|
100.00 |
|
|
|
u_tlul_data_integ_dec |
100.00 |
100.00 |
|
100.00 |
|
|
|
u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
u_cmd_cmd |
100.00 |
100.00 |
|
|
|
|
|
u_cmd_entropy_req |
100.00 |
100.00 |
|
|
|
|
|
u_cmd_err_processed |
100.00 |
100.00 |
|
|
|
|
|
u_cmd_hash_cnt_clr |
100.00 |
100.00 |
|
|
|
|
|
u_entropy_period_prescaler |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_entropy_period_wait_timer |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_entropy_refresh_hash_cnt |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_entropy_refresh_threshold_shadowed |
98.66 |
100.00 |
94.64 |
|
|
100.00 |
100.00 |
committed_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
shadow_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
staged_reg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_entropy_seed |
100.00 |
100.00 |
|
|
|
|
|
u_err_code |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
|
|
|
|
|
u_intr_enable_fifo_empty |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_kmac_done |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_kmac_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_state_fifo_empty |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_intr_state_kmac_done |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_kmac_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_test_fifo_empty |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_kmac_done |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_kmac_err |
100.00 |
100.00 |
|
|
|
|
|
u_key_len |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_key_share0_0 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_1 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_10 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_11 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_12 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_13 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_14 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_15 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_2 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_3 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_4 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_5 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_6 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_7 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_8 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share0_9 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_0 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_1 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_10 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_11 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_12 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_13 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_14 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_15 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_2 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_3 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_4 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_5 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_6 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_7 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_8 |
100.00 |
100.00 |
|
|
|
|
|
u_key_share1_9 |
100.00 |
100.00 |
|
|
|
|
|
u_prefix_0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_prefix_1 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_prefix_10 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_prefix_2 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_prefix_3 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_prefix_4 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_prefix_5 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_prefix_6 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_prefix_7 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_prefix_8 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_prefix_9 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_prim_reg_we_check |
50.00 |
100.00 |
|
0.00 |
|
|
|
u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_onehot_check |
0.00 |
|
|
0.00 |
|
|
|
u_reg_if |
98.69 |
97.14 |
97.62 |
|
|
100.00 |
100.00 |
u_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_rsp_intg_gen |
83.33 |
66.67 |
|
|
|
|
100.00 |
u_rsp_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|
u_socket |
93.69 |
96.05 |
89.53 |
|
|
89.19 |
100.00 |
fifo_h |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
reqfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
rspfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_dfifo[0].fifo_d |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
reqfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
rspfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_dfifo[1].fifo_d |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
reqfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
rspfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_dfifo[2].fifo_d |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
reqfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
rspfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_err_resp.err_resp |
71.59 |
86.36 |
50.00 |
|
|
50.00 |
100.00 |
u_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|
u_status_alert_fatal_fault |
100.00 |
100.00 |
|
|
|
|
|
u_status_alert_recov_ctrl_update_err |
100.00 |
100.00 |
|
|
|
|
|
u_status_fifo_depth |
100.00 |
100.00 |
|
|
|
|
|
u_status_fifo_empty |
100.00 |
100.00 |
|
|
|
|
|
u_status_fifo_full |
100.00 |
100.00 |
|
|
|
|
|
u_status_sha3_absorb |
33.33 |
33.33 |
|
|
|
|
|
u_status_sha3_idle |
100.00 |
100.00 |
|
|
|
|
|
u_status_sha3_squeeze |
33.33 |
33.33 |
|
|
|
|
|