Unified Coverage Report :: Module Instance :: tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_tlul_adapter_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00

Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_tlul_adapter_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00

Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_tlul_adapter_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00

Module Instance : tb.dut.u_msgfifo.u_msgfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00			0.00	0.00		u_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00	0.00		0.00

Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00

Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00

Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
ALWAYS	69	4	0	0.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	101	1	0	0.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	138	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	0	1
70	0	1
71	0	1
72	0	1
			==> MISSING_ELSE
81	0	1
82	0	1
100	0	1
101	0	1
108	0	1
111	0	1
112	0	1
			==> MISSING_ELSE
116	0	1
133	0	1
134	0	1
138	0	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Total	Covered	Percent
Conditions	16	0	0.00
Logical	16	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	0	0.00
TERNARY	138	2	0	0.00
IF	69	3	0	0.00
IF	111	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	69	4	0	0.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	101	0	0
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	138	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	0	1
70	0	1
71	0	1
72	0	1
			==> MISSING_ELSE
81	0	1
82	0	1
100	0	1
101		unreachable
108	0	1
111	0	1
112	0	1
			==> MISSING_ELSE
116	0	1
133	0	1
134	0	1
138	0	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Total	Covered	Percent
Conditions	13	0	0.00
Logical	13	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Not Covered
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	0	0.00
TERNARY	138	2	0	0.00
IF	69	3	0	0.00
IF	111	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		13	0	0.00
ALWAYS	69	4	0	0.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	100	0	0
CONT_ASSIGN	101	1	0	0.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	1	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	130	1	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	138	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	0	1
70	0	1
71	0	1
72	0	1
			==> MISSING_ELSE
81	0	1
82	0	1
100		unreachable
101	0	1
108	0	1
111	0	1
112		unreachable
			==> MISSING_ELSE
116	0	1
130	0	1
131	0	1
138	0	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Total	Covered	Percent
Conditions	17	0	0.00
Logical	17	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Unreachable

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		7	0	0.00
TERNARY	130	1	0	0.00
TERNARY	138	2	0	0.00
IF	69	3	0	0.00
IF	111	1	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Unreachable
0	Not Covered

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Unreachable
0	Not Covered

Line Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	69	4	0	0.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	101	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
ALWAYS	123	2	0	0.00
CONT_ASSIGN	130	1	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	138	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	0	1
70	0	1
71	0	1
72	0	1
			==> MISSING_ELSE
81	0	1
82	0	1
100	0	1
101	0	1
120	0	1
123	0	1
124	0	1
			==> MISSING_ELSE
130	0	1
131	0	1
138	0	1

---

Cond Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Total	Covered	Percent
Conditions	24	0	0.00
Logical	24	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (72'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo

	Line No.	Total	Covered	Percent
Branches		9	0	0.00
TERNARY	130	2	0	0.00
TERNARY	138	2	0	0.00
IF	69	3	0	0.00
IF	111	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
ALWAYS	69	4	0	0.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	101	1	0	0.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	138	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	0	1
70	0	1
71	0	1
72	0	1
			==> MISSING_ELSE
81	0	1
82	0	1
100	0	1
101	0	1
108	0	1
111	0	1
112	0	1
			==> MISSING_ELSE
116	0	1
133	0	1
134	0	1
138	0	1

---

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Total	Covered	Percent
Conditions	16	0	0.00
Logical	16	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	0	0.00
TERNARY	138	2	0	0.00
IF	69	3	0	0.00
IF	111	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
ALWAYS	69	4	0	0.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	101	1	0	0.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	138	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	0	1
70	0	1
71	0	1
72	0	1
			==> MISSING_ELSE
81	0	1
82	0	1
100	0	1
101	0	1
108	0	1
111	0	1
112	0	1
			==> MISSING_ELSE
116	0	1
133	0	1
134	0	1
138	0	1

---

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	0	0.00
Logical	16	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	0	0.00
TERNARY	138	2	0	0.00
IF	69	3	0	0.00
IF	111	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
ALWAYS	69	4	0	0.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	101	1	0	0.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	130	1	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	138	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	0	1
70	0	1
71	0	1
72	0	1
			==> MISSING_ELSE
81	0	1
82	0	1
100	0	1
101	0	1
108	0	1
111	0	1
112	0	1
			==> MISSING_ELSE
116	0	1
130	0	1
131	0	1
138	0	1

---

Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Total	Covered	Percent
Conditions	24	0	0.00
Logical	24	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	0	0.00
TERNARY	130	2	0	0.00
TERNARY	138	2	0	0.00
IF	69	3	0	0.00
IF	111	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1329833	322572	0	0
DepthKnown_A	1329833	1281208	0	0
RvalidKnown_A	1329833	1281208	0	0
WreadyKnown_A	1329833	1281208	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	322572	0	0
T1	10763	1360	0	0
T2	2910	2056	0	0
T3	1105	22	0	0
T4	24067	5666	0	0
T5	8880	1379	0	0
T9	1477	38	0	0
T12	5149	706	0	0
T13	11733	3341	0	0
T14	1480	230	0	0
T15	9853	1541	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1329833	348380	0	0
DepthKnown_A	1329833	1281208	0	0
RvalidKnown_A	1329833	1281208	0	0
WreadyKnown_A	1329833	1281208	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	348380	0	0
T1	10763	1263	0	0
T2	2910	913	0	0
T3	1105	22	0	0
T4	24067	12035	0	0
T5	8880	1217	0	0
T9	1477	38	0	0
T12	5149	652	0	0
T13	11733	6488	0	0
T14	1480	117	0	0
T15	9853	1282	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1329833	17186	0	0
DepthKnown_A	1329833	1281208	0	0
RvalidKnown_A	1329833	1281208	0	0
WreadyKnown_A	1329833	1281208	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	17186	0	0
T2	2910	511	0	0
T3	1105	0	0	0
T4	24067	0	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T12	5149	0	0	0
T13	11733	0	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	9	0	0
T18	0	19	0	0
T20	0	412	0	0
T21	0	8	0	0
T22	0	1514	0	0
T23	0	10	0	0
T24	0	298	0	0
T25	0	1084	0	0
T26	0	1064	0	0
T27	9433	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1329833	16363	0	0
DepthKnown_A	1329833	1281208	0	0
RvalidKnown_A	1329833	1281208	0	0
WreadyKnown_A	1329833	1281208	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	16363	0	0
T2	2910	249	0	0
T3	1105	0	0	0
T4	24067	0	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T12	5149	0	0	0
T13	11733	0	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	20	0	0
T18	0	51	0	0
T20	0	899	0	0
T21	0	4	0	0
T22	0	2974	0	0
T23	0	5	0	0
T24	0	144	0	0
T25	0	508	0	0
T26	0	501	0	0
T27	9433	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1329833	23372	0	0
DepthKnown_A	1329833	1281208	0	0
RvalidKnown_A	1329833	1281208	0	0
WreadyKnown_A	1329833	1281208	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	23372	0	0
T2	2910	391	0	0
T3	1105	0	0	0
T4	24067	0	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T12	5149	0	0	0
T13	11733	0	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T16	0	841	0	0
T17	0	489	0	0
T18	0	1013	0	0
T19	0	401	0	0
T20	0	117	0	0
T21	0	230	0	0
T22	0	611	0	0
T27	9433	0	0	0
T28	0	505	0	0
T29	0	864	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1329833	36403	0	0
DepthKnown_A	1329833	1281208	0	0
RvalidKnown_A	1329833	1281208	0	0
WreadyKnown_A	1329833	1281208	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	36403	0	0
T2	2910	323	0	0
T3	1105	0	0	0
T4	24067	0	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T12	5149	0	0	0
T13	11733	0	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T16	0	1704	0	0
T17	0	1022	0	0
T18	0	2010	0	0
T19	0	370	0	0
T20	0	486	0	0
T21	0	214	0	0
T22	0	2361	0	0
T27	9433	0	0	0
T28	0	253	0	0
T29	0	1764	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1281208	0	0
T1	10763	9969	0	0
T2	2910	2840	0	0
T3	1105	1023	0	0
T4	24067	22494	0	0
T5	8880	8518	0	0
T9	1477	1399	0	0
T12	5149	4945	0	0
T13	11733	10954	0	0
T14	1480	1404	0	0
T15	9853	9410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0