Module Definition
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Module : prim_packer
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_msgfifo.u_packer 0.00 0.00 0.00 0.00


Module Instance : tb.dut.u_msgfifo.u_packer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 u_msgfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_pos_dupcnt.u_pos 0.00 0.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_packer
Line No.TotalCoveredPercent
TOTAL6200.00
ALWAYS65300.00
CONT_ASSIGN72100.00
CONT_ASSIGN110100.00
CONT_ASSIGN111100.00
CONT_ASSIGN112100.00
CONT_ASSIGN115100.00
ALWAYS120300.00
ALWAYS157400.00
CONT_ASSIGN165100.00
CONT_ASSIGN166100.00
CONT_ASSIGN170100.00
CONT_ASSIGN171100.00
CONT_ASSIGN174100.00
CONT_ASSIGN175100.00
CONT_ASSIGN178100.00
CONT_ASSIGN180100.00
ALWAYS185900.00
ALWAYS214800.00
ALWAYS235300.00
ALWAYS2431400.00
CONT_ASSIGN279100.00
CONT_ASSIGN283100.00
CONT_ASSIGN29100
CONT_ASSIGN294100.00
CONT_ASSIGN295100.00
CONT_ASSIGN296100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 0 1
66 0 1
67 0 1
72 0 1
110 0 1
111 0 1
112 0 1
115 0 1
120 0 1
122 0 1
124 0 1
==> MISSING_ELSE
157 0 1
158 0 1
159 0 1
160 0 1
==> MISSING_ELSE
165 0 1
166 0 1
170 0 1
171 0 1
174 0 1
175 0 1
178 0 1
180 0 1
185 0 1
187 0 1
188 0 1
192 0 1
193 0 1
197 0 1
198 0 1
202 0 1
203 0 1
214 0 1
215 0 1
216 0 1
217 0 1
218 0 1
219 0 1
221 0 1
222 0 1
235 0 1
236 0 1
238 0 1
243 0 1
245 0 1
246 0 1
248 0 1
250 0 1
251 0 1
253 0 1
258 0 1
259 0 1
261 0 1
262 0 1
264 0 1
266 0 1
267 0 1
279 0 1
283 0 1
291 unreachable
294 0 1
295 0 1
296 0 1
299 unreachable

Cond Coverage for Module : prim_packer
TotalCoveredPercent
Conditions2500.00
Logical2500.00
Non-Logical00
Event00

 LINE       110
 EXPRESSION (ack_in && ((!ack_out)))
             ---1--    ------2-----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       111
 EXPRESSION (((!ack_in)) && ack_out)
             -----1-----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       112
 EXPRESSION (ack_in && ack_out)
             ---1--    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       115
 EXPRESSION (g_pos_dupcnt.cnt_incr_en ? (8'(inmask_ones)) : (8'(OutW)))
             ------------1-----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       159
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       165
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---
-1--2-StatusTests
01Not Covered
10Unreachable
11Not Covered 

 LINE       166
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       170
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       171
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       258
 EXPRESSION (pos_q == '0)
            ------1------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       283
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------
-1-StatusTests
0Not Covered
1Unreachable
Branch Coverage for Module : prim_packer
Line No.TotalCoveredPercent
Branches 26 0 0.00
TERNARY 170 2 0 0.00
TERNARY 171 2 0 0.00
TERNARY 283 1 0 0.00
TERNARY 115 2 0 0.00
IF 159 2 0 0.00
CASE 185 5 0 0.00
IF 214 3 0 0.00
IF 235 2 0 0.00
CASE 248 5 0 0.00
IF 122 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	170	(valid_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	171	(valid_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	283	((int'(pos_q) >= OutW)) ?

Branches:
-1-StatusTests
1 Unreachable
0 Not Covered 



	LineNo.	Expression
-1-:	115	(g_pos_dupcnt.cnt_incr_en) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	159	if ((mask_i[i] == 1'b1))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	185	case ({ack_in, ack_out})

Branches:
-1-StatusTests
2'b00 Not Covered
2'b01 Not Covered
2'b10 Not Covered
2'b11 Not Covered
default Not Covered 



	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	217	if (flush_done)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	235	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	248	case (flush_st)
-2-:	250	if (flush_i)
-3-:	258	if ((pos_q == '0))

Branches:
-1--2--3-StatusTests
FlushIdle 1 - Not Covered
FlushIdle 0 - Not Covered
FlushSend - 1 Not Covered
FlushSend - 0 Not Covered
default - - Not Covered 



	LineNo.	Expression
-1-:	122	if ((pos_with_input > 8'(OutW)))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

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