Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
1.32	0.00	0.00	6.61	0.00	0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1329833	3712	0	0
entropy_period_rd_A	1329833	1505	0	0
intr_enable_rd_A	1329833	1777	0	0
prefix_0_rd_A	1329833	1355	0	0
prefix_10_rd_A	1329833	1242	0	0
prefix_1_rd_A	1329833	1170	0	0
prefix_2_rd_A	1329833	1445	0	0
prefix_3_rd_A	1329833	1346	0	0
prefix_4_rd_A	1329833	1188	0	0
prefix_5_rd_A	1329833	1275	0	0
prefix_6_rd_A	1329833	1358	0	0
prefix_7_rd_A	1329833	1186	0	0
prefix_8_rd_A	1329833	1307	0	0
prefix_9_rd_A	1329833	1305	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	3712	0	0
T1	10763	1	0	0
T2	2910	90	0	0
T3	1105	0	0	0
T4	24067	2	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T12	5149	0	0	0
T13	11733	0	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	1	0	0
T18	0	4	0	0
T20	0	27	0	0
T27	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1505	0	0
T4	24067	106	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T10	1714	0	0	0
T11	1342	0	0	0
T12	5149	0	0	0
T13	11733	56	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	15	0	0
T18	0	14	0	0
T27	9433	0	0	0
T34	0	32	0	0
T37	0	21	0	0
T48	0	33	0	0
T49	0	6	0	0
T52	0	38	0	0
T53	0	22	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1777	0	0
T4	24067	127	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T10	1714	15	0	0
T11	1342	0	0	0
T12	5149	0	0	0
T13	11733	91	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	3	0	0
T18	0	29	0	0
T27	9433	0	0	0
T37	0	11	0	0
T43	0	5	0	0
T44	0	11	0	0
T49	0	19	0	0
T62	0	8	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1355	0	0
T4	24067	67	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T10	1714	0	0	0
T11	1342	0	0	0
T12	5149	0	0	0
T13	11733	24	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	9	0	0
T18	0	8	0	0
T27	9433	0	0	0
T34	0	28	0	0
T48	0	34	0	0
T49	0	3	0	0
T50	0	57	0	0
T52	0	32	0	0
T53	0	25	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1242	0	0
T4	24067	95	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T10	1714	0	0	0
T11	1342	0	0	0
T12	5149	0	0	0
T13	11733	53	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	8	0	0
T18	0	20	0	0
T27	9433	0	0	0
T34	0	27	0	0
T37	0	39	0	0
T48	0	55	0	0
T49	0	14	0	0
T52	0	31	0	0
T53	0	8	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1170	0	0
T4	24067	87	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T10	1714	0	0	0
T11	1342	0	0	0
T12	5149	0	0	0
T13	11733	50	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	4	0	0
T18	0	3	0	0
T27	9433	0	0	0
T34	0	14	0	0
T37	0	8	0	0
T48	0	29	0	0
T49	0	17	0	0
T52	0	15	0	0
T53	0	12	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1445	0	0
T4	24067	90	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T10	1714	0	0	0
T11	1342	0	0	0
T12	5149	0	0	0
T13	11733	47	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	5	0	0
T18	0	24	0	0
T27	9433	0	0	0
T34	0	40	0	0
T37	0	36	0	0
T48	0	116	0	0
T50	0	68	0	0
T52	0	34	0	0
T53	0	9	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1346	0	0
T4	24067	78	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T10	1714	0	0	0
T11	1342	0	0	0
T12	5149	0	0	0
T13	11733	57	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	12	0	0
T18	0	11	0	0
T27	9433	0	0	0
T34	0	15	0	0
T37	0	47	0	0
T48	0	21	0	0
T49	0	15	0	0
T52	0	57	0	0
T53	0	11	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1188	0	0
T4	24067	76	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T10	1714	0	0	0
T11	1342	0	0	0
T12	5149	0	0	0
T13	11733	48	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	4	0	0
T18	0	19	0	0
T27	9433	0	0	0
T34	0	7	0	0
T37	0	22	0	0
T48	0	16	0	0
T49	0	11	0	0
T52	0	26	0	0
T53	0	21	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1275	0	0
T4	24067	75	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T10	1714	0	0	0
T11	1342	0	0	0
T12	5149	0	0	0
T13	11733	61	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T18	0	23	0	0
T27	9433	0	0	0
T34	0	34	0	0
T37	0	1	0	0
T48	0	57	0	0
T49	0	13	0	0
T50	0	55	0	0
T52	0	25	0	0
T53	0	20	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1358	0	0
T4	24067	56	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T10	1714	0	0	0
T11	1342	0	0	0
T12	5149	0	0	0
T13	11733	52	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	17	0	0
T18	0	14	0	0
T27	9433	0	0	0
T34	0	40	0	0
T48	0	82	0	0
T50	0	44	0	0
T52	0	37	0	0
T53	0	12	0	0
T63	0	44	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1186	0	0
T4	24067	70	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T10	1714	0	0	0
T11	1342	0	0	0
T12	5149	0	0	0
T13	11733	31	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	3	0	0
T18	0	15	0	0
T27	9433	0	0	0
T34	0	12	0	0
T37	0	31	0	0
T48	0	62	0	0
T49	0	12	0	0
T52	0	45	0	0
T53	0	25	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1307	0	0
T4	24067	57	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T10	1714	0	0	0
T11	1342	0	0	0
T12	5149	0	0	0
T13	11733	44	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	12	0	0
T18	0	9	0	0
T27	9433	0	0	0
T34	0	35	0	0
T37	0	8	0	0
T48	0	90	0	0
T49	0	10	0	0
T52	0	45	0	0
T53	0	10	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1329833	1305	0	0
T4	24067	79	0	0
T5	8880	0	0	0
T9	1477	0	0	0
T10	1714	0	0	0
T11	1342	0	0	0
T12	5149	0	0	0
T13	11733	36	0	0
T14	1480	0	0	0
T15	9853	0	0	0
T17	0	3	0	0
T18	0	21	0	0
T27	9433	0	0	0
T34	0	18	0	0
T37	0	36	0	0
T48	0	17	0	0
T49	0	10	0	0
T52	0	29	0	0
T53	0	10	0	0