Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169993 |
1 |
|
|
T1 |
268 |
|
T7 |
281 |
|
T8 |
100 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
91129 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
57147 |
1 |
|
|
T1 |
264 |
|
T7 |
7 |
|
T8 |
98 |
seven_bytes |
3166 |
1 |
|
|
T7 |
4 |
|
T17 |
78 |
|
T18 |
59 |
six_bytes |
3163 |
1 |
|
|
T7 |
9 |
|
T17 |
67 |
|
T18 |
62 |
five_bytes |
3128 |
1 |
|
|
T7 |
8 |
|
T17 |
73 |
|
T18 |
70 |
four_bytes |
3083 |
1 |
|
|
T7 |
5 |
|
T17 |
69 |
|
T18 |
55 |
three_bytes |
3001 |
1 |
|
|
T7 |
11 |
|
T17 |
70 |
|
T18 |
53 |
two_bytes |
3033 |
1 |
|
|
T7 |
10 |
|
T17 |
62 |
|
T18 |
64 |
one_byte |
3143 |
1 |
|
|
T7 |
9 |
|
T17 |
54 |
|
T18 |
65 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
166847 |
1 |
|
|
T1 |
260 |
|
T7 |
279 |
|
T8 |
96 |
auto[1] |
3146 |
1 |
|
|
T1 |
8 |
|
T7 |
2 |
|
T8 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169993 |
1 |
|
|
T1 |
268 |
|
T7 |
281 |
|
T8 |
100 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169982 |
1 |
|
|
T1 |
268 |
|
T7 |
281 |
|
T8 |
100 |
auto[1] |
11 |
1 |
|
|
T96 |
1 |
|
T172 |
1 |
|
T58 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1058 |
1 |
|
|
T1 |
4 |
|
T8 |
2 |
|
T17 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3146 |
1 |
|
|
T1 |
8 |
|
T7 |
2 |
|
T8 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167501 |
1 |
|
|
T1 |
182 |
|
T8 |
48 |
|
T20 |
216 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
87446 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
59197 |
1 |
|
|
T1 |
177 |
|
T8 |
47 |
|
T20 |
214 |
seven_bytes |
2961 |
1 |
|
|
T17 |
65 |
|
T18 |
60 |
|
T42 |
63 |
six_bytes |
2988 |
1 |
|
|
T17 |
60 |
|
T18 |
54 |
|
T42 |
58 |
five_bytes |
3034 |
1 |
|
|
T17 |
61 |
|
T18 |
61 |
|
T42 |
66 |
four_bytes |
3000 |
1 |
|
|
T17 |
60 |
|
T18 |
42 |
|
T42 |
67 |
three_bytes |
3002 |
1 |
|
|
T17 |
72 |
|
T18 |
60 |
|
T42 |
62 |
two_bytes |
2960 |
1 |
|
|
T17 |
61 |
|
T18 |
62 |
|
T42 |
64 |
one_byte |
2913 |
1 |
|
|
T17 |
58 |
|
T18 |
57 |
|
T42 |
52 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164305 |
1 |
|
|
T1 |
172 |
|
T8 |
46 |
|
T20 |
212 |
auto[1] |
3196 |
1 |
|
|
T1 |
10 |
|
T8 |
2 |
|
T20 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167501 |
1 |
|
|
T1 |
182 |
|
T8 |
48 |
|
T20 |
216 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167498 |
1 |
|
|
T1 |
182 |
|
T8 |
48 |
|
T20 |
216 |
auto[1] |
3 |
1 |
|
|
T173 |
1 |
|
T174 |
1 |
|
T175 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1091 |
1 |
|
|
T1 |
5 |
|
T8 |
1 |
|
T20 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3196 |
1 |
|
|
T1 |
10 |
|
T8 |
2 |
|
T20 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
333976 |
1 |
|
|
T1 |
184 |
|
T8 |
59 |
|
T20 |
62 |
auto[1] |
529 |
1 |
|
|
T6 |
83 |
|
T9 |
47 |
|
T10 |
3 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
176808 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
115840 |
1 |
|
|
T1 |
182 |
|
T8 |
58 |
|
T20 |
61 |
seven_bytes |
5940 |
1 |
|
|
T17 |
109 |
|
T18 |
86 |
|
T42 |
110 |
six_bytes |
6109 |
1 |
|
|
T17 |
100 |
|
T18 |
101 |
|
T42 |
99 |
five_bytes |
6030 |
1 |
|
|
T17 |
106 |
|
T18 |
117 |
|
T42 |
118 |
four_bytes |
5817 |
1 |
|
|
T17 |
101 |
|
T18 |
89 |
|
T42 |
109 |
three_bytes |
6017 |
1 |
|
|
T17 |
98 |
|
T18 |
92 |
|
T42 |
109 |
two_bytes |
5963 |
1 |
|
|
T17 |
86 |
|
T18 |
93 |
|
T42 |
116 |
one_byte |
5981 |
1 |
|
|
T17 |
100 |
|
T18 |
103 |
|
T42 |
105 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
328061 |
1 |
|
|
T1 |
180 |
|
T8 |
57 |
|
T20 |
60 |
auto[1] |
6444 |
1 |
|
|
T1 |
4 |
|
T8 |
2 |
|
T20 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
334505 |
1 |
|
|
T1 |
184 |
|
T8 |
59 |
|
T20 |
62 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
334476 |
1 |
|
|
T1 |
184 |
|
T8 |
59 |
|
T20 |
62 |
auto[1] |
29 |
1 |
|
|
T43 |
1 |
|
T96 |
1 |
|
T176 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2174 |
1 |
|
|
T1 |
2 |
|
T8 |
1 |
|
T20 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6444 |
1 |
|
|
T1 |
4 |
|
T8 |
2 |
|
T20 |
2 |