Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43931461	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

43563705

1

T1

15974

T2

294809

T3

10557

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48415577	1			T1	21068		T2	382296		T3	14115
values[0x0]	18936652	1			T1	4370		T2	169871		T3	3393
values[0x1]	20142937	1			T1	4713		T2	184767		T3	3662

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33747890	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

53747276

1

T1

19571

T2

392498

T3

13200

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	274549	1			T1	6		T2	322		T3	73
valid_sources[0x01]	272549	1			T1	7		T2	347		T3	68
valid_sources[0x02]	309465	1			T1	7		T2	312		T3	86
valid_sources[0x03]	272041	1			T1	7		T2	325		T3	88
valid_sources[0x04]	294692	1			T1	8		T2	368		T3	68
valid_sources[0x05]	272795	1			T1	5		T2	348		T3	70
valid_sources[0x06]	297380	1			T1	7		T2	315		T3	85
valid_sources[0x07]	277441	1			T1	4		T2	316		T3	96
valid_sources[0x08]	359496	1			T1	12		T2	352		T3	109
valid_sources[0x09]	281191	1			T1	10		T2	345		T3	119
valid_sources[0x0a]	429372	1			T1	9		T2	342		T3	65
valid_sources[0x0b]	273744	1			T1	7		T2	329		T3	65
valid_sources[0x0c]	307726	1			T1	9		T2	363		T3	71
valid_sources[0x0d]	274690	1			T1	12		T2	342		T3	122
valid_sources[0x0e]	274792	1			T1	11		T2	364		T3	54
valid_sources[0x0f]	280603	1			T1	6		T2	348		T3	104
valid_sources[0x10]	348170	1			T1	5		T2	333		T3	83
valid_sources[0x11]	274646	1			T1	8		T2	343		T3	73
valid_sources[0x12]	1062424	1			T1	5		T2	336		T3	71
valid_sources[0x13]	276997	1			T1	4		T2	324		T3	68
valid_sources[0x14]	326980	1			T1	3		T2	353		T3	96
valid_sources[0x15]	280605	1			T1	11		T2	330		T3	79
valid_sources[0x16]	911469	1			T1	8		T2	345		T3	75
valid_sources[0x17]	274034	1			T1	9		T2	320		T3	87
valid_sources[0x18]	275585	1			T1	11		T2	328		T3	73
valid_sources[0x19]	417940	1			T1	5		T2	341		T3	79
valid_sources[0x1a]	275525	1			T1	8		T2	349		T3	71
valid_sources[0x1b]	275960	1			T1	7		T2	340		T3	70
valid_sources[0x1c]	275029	1			T1	6		T2	332		T3	96
valid_sources[0x1d]	280731	1			T1	6		T2	336		T3	116
valid_sources[0x1e]	277594	1			T1	9		T2	324		T3	116
valid_sources[0x1f]	353329	1			T1	4		T2	331		T3	84
valid_sources[0x20]	275679	1			T1	4		T2	361		T3	71
valid_sources[0x21]	292804	1			T1	6		T2	356		T3	79
valid_sources[0x22]	274924	1			T1	7		T2	350		T3	64
valid_sources[0x23]	272975	1			T1	5		T2	327		T3	81
valid_sources[0x24]	355767	1			T1	7		T2	331		T3	84
valid_sources[0x25]	276998	1			T1	8		T2	316		T3	67
valid_sources[0x26]	275232	1			T1	10		T2	368		T3	113
valid_sources[0x27]	279654	1			T1	6		T2	341		T3	85
valid_sources[0x28]	272726	1			T1	10		T2	346		T3	69
valid_sources[0x29]	967380	1			T1	4		T2	333		T3	70
valid_sources[0x2a]	273488	1			T1	3		T2	295		T3	81
valid_sources[0x2b]	278841	1			T1	9		T2	333		T3	89
valid_sources[0x2c]	276581	1			T1	4		T2	343		T3	70
valid_sources[0x2d]	277344	1			T1	8		T2	307		T3	85
valid_sources[0x2e]	281458	1			T1	4		T2	331		T3	98
valid_sources[0x2f]	278317	1			T1	2		T2	353		T3	58
valid_sources[0x30]	275618	1			T1	7		T2	342		T3	84
valid_sources[0x31]	276873	1			T1	7		T2	332		T3	84
valid_sources[0x32]	415791	1			T1	3		T2	352		T3	80
valid_sources[0x33]	275439	1			T1	8		T2	326		T3	103
valid_sources[0x34]	278970	1			T1	5		T2	335		T3	68
valid_sources[0x35]	275400	1			T1	6		T2	371		T3	90
valid_sources[0x36]	340562	1			T1	7		T2	365		T3	113
valid_sources[0x37]	278230	1			T1	1		T2	345		T3	83
valid_sources[0x38]	394322	1			T1	3		T2	334		T3	85
valid_sources[0x39]	280634	1			T1	5		T2	339		T3	67
valid_sources[0x3a]	273923	1			T1	7		T2	351		T3	76
valid_sources[0x3b]	942460	1			T1	4		T2	334		T3	69
valid_sources[0x3c]	315940	1			T1	7		T2	333		T3	81
valid_sources[0x3d]	291179	1			T1	10		T2	311		T3	102
valid_sources[0x3e]	281213	1			T1	10		T2	360		T3	75
valid_sources[0x3f]	274986	1			T2	337		T3	71		T36	103
valid_sources[0x40]	277462	1			T1	8		T2	368		T3	71
valid_sources[0x41]	276510	1			T1	5		T2	313		T3	96
valid_sources[0x42]	341634	1			T1	9		T2	319		T3	90
valid_sources[0x43]	1272210	1			T1	9		T2	325		T3	79
valid_sources[0x44]	356880	1			T1	6		T2	348		T3	101
valid_sources[0x45]	288382	1			T1	10		T2	331		T3	80
valid_sources[0x46]	1130717	1			T1	4		T2	650862		T3	101
valid_sources[0x47]	724648	1			T1	12		T2	329		T3	61
valid_sources[0x48]	423563	1			T1	8		T2	377		T3	78
valid_sources[0x49]	276536	1			T1	4		T2	321		T3	98
valid_sources[0x4a]	279243	1			T1	8		T2	346		T3	50
valid_sources[0x4b]	290043	1			T1	4		T2	391		T3	88
valid_sources[0x4c]	370772	1			T1	7		T2	343		T3	98
valid_sources[0x4d]	279158	1			T1	7		T2	335		T3	59
valid_sources[0x4e]	349690	1			T1	9		T2	348		T3	92
valid_sources[0x4f]	423415	1			T1	8		T2	321		T3	88
valid_sources[0x50]	302727	1			T1	9		T2	320		T3	95
valid_sources[0x51]	274226	1			T1	6		T2	337		T3	63
valid_sources[0x52]	1129209	1			T1	3		T2	364		T3	81
valid_sources[0x53]	274675	1			T1	7		T2	317		T3	70
valid_sources[0x54]	276285	1			T1	6		T2	318		T3	91
valid_sources[0x55]	331803	1			T1	6		T2	311		T3	75
valid_sources[0x56]	273976	1			T1	5		T2	343		T3	94
valid_sources[0x57]	281617	1			T1	9		T2	356		T3	98
valid_sources[0x58]	279033	1			T1	10		T2	297		T3	98
valid_sources[0x59]	276788	1			T1	2		T2	363		T3	73
valid_sources[0x5a]	279571	1			T1	4		T2	347		T3	84
valid_sources[0x5b]	279175	1			T1	11		T2	322		T3	82
valid_sources[0x5c]	276560	1			T1	10		T2	321		T3	77
valid_sources[0x5d]	277974	1			T1	9		T2	318		T3	80
valid_sources[0x5e]	400667	1			T1	8		T2	325		T3	100
valid_sources[0x5f]	395406	1			T1	5		T2	392		T3	92
valid_sources[0x60]	273823	1			T1	9		T2	353		T3	78
valid_sources[0x61]	275219	1			T1	3		T2	319		T3	101
valid_sources[0x62]	290899	1			T1	6		T2	311		T3	68
valid_sources[0x63]	292914	1			T1	8		T2	322		T3	96
valid_sources[0x64]	305708	1			T1	6		T2	354		T3	74
valid_sources[0x65]	275843	1			T1	8		T2	328		T3	72
valid_sources[0x66]	277474	1			T1	3		T2	357		T3	73
valid_sources[0x67]	410087	1			T1	6		T2	350		T3	104
valid_sources[0x68]	279092	1			T1	7		T2	317		T3	69
valid_sources[0x69]	278579	1			T1	11		T2	329		T3	59
valid_sources[0x6a]	275577	1			T1	7		T2	348		T3	90
valid_sources[0x6b]	432774	1			T1	8		T2	334		T3	72
valid_sources[0x6c]	278089	1			T1	7		T2	318		T3	89
valid_sources[0x6d]	278474	1			T1	7		T2	350		T3	85
valid_sources[0x6e]	278177	1			T1	6		T2	342		T3	68
valid_sources[0x6f]	281465	1			T1	9		T2	368		T3	62
valid_sources[0x70]	279056	1			T1	9		T2	342		T3	85
valid_sources[0x71]	275929	1			T1	5		T2	333		T3	102
valid_sources[0x72]	278588	1			T1	6		T2	340		T3	112
valid_sources[0x73]	274662	1			T1	10		T2	367		T3	78
valid_sources[0x74]	277572	1			T1	7		T2	322		T3	111
valid_sources[0x75]	350976	1			T1	8		T2	345		T3	60
valid_sources[0x76]	277543	1			T1	8		T2	331		T3	95
valid_sources[0x77]	275632	1			T1	12		T2	334		T3	82
valid_sources[0x78]	275283	1			T1	3		T2	313		T3	93
valid_sources[0x79]	277207	1			T1	6		T2	317		T3	73
valid_sources[0x7a]	277725	1			T1	7		T2	351		T3	104
valid_sources[0x7b]	278087	1			T1	6		T2	340		T3	79
valid_sources[0x7c]	279110	1			T1	7		T2	325		T3	81
valid_sources[0x7d]	291821	1			T1	7		T2	320		T3	94
valid_sources[0x7e]	1420913	1			T1	9		T2	334		T3	107
valid_sources[0x7f]	277265	1			T1	6		T2	321		T3	109
valid_sources[0x80]	273176	1			T1	9		T2	328		T3	85

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19117491

1

T1

10730

T2

117191

T3

6665

values[0x0]

all_enables

biggest_size

12829897

1

T1

2827

T2

96050

T3

2086

values[0x1]

all_enables

biggest_size

11616317

1

T1

2417

T2

81568

T3

1806