Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43971849

1

T1

14177

T2

442125

T3

10613

full_word

43566251

1

T1

15974

T2

294809

T3

10557

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	87537800	1			T1	30151		T2	736934		T3	21170
auto[TlIntgErrCmd]	98	1			T116	10		T117	3		T177	6
auto[TlIntgErrData]	96	1			T116	2		T117	3		T118	3
auto[TlIntgErrBoth]	106	1			T116	8		T117	4		T118	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48424827

1

T1

21068

T2

382296

T3

14115

auto[1]

39113273

1

T1

9083

T2

354638

T3

7055

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	29306529	1			T1	10338		T2	265105		T3	7450
auto[TlIntgErrNone]	partial	auto[1]	14665035	1			T1	3839		T2	177020		T3	3163
auto[TlIntgErrNone]	full_word	auto[0]	19118178	1			T1	10730		T2	117191		T3	6665
auto[TlIntgErrNone]	full_word	auto[1]	24448058	1			T1	5244		T2	177618		T3	3892
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T116	5		T117	1		T177	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T116	4		T117	2		T177	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T178	1		T179	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T116	1		T178	1		T180	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T116	1		T117	1		T118	1
auto[TlIntgErrData]	partial	auto[1]	53	1			T116	1		T117	2		T118	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T118	1		T181	1		T182	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T183	1		T184	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T116	2		T117	1		T177	3
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T116	5		T117	3		T118	7
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T116	1		T178	1		T185	1