Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	505998686	50499	0	0
RunThenComplete_M	505998686	666084	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505998686	50499	0	0
T1	87242	35	0	0
T2	742737	94	0	0
T3	52237	19	0	0
T7	15252	1	0	0
T8	133821	17	0	0
T21	34101	10	0	0
T36	245398	143	0	0
T37	705461	100	0	0
T38	882759	18	0	0
T39	125220	70	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	505998686	666084	0	0
T1	87242	175	0	0
T2	742737	4232	0	0
T3	52237	90	0	0
T7	15252	7	0	0
T8	133821	84	0	0
T21	34101	44	0	0
T36	245398	375	0	0
T37	705461	5250	0	0
T38	882759	745	0	0
T39	125220	182	0	0