Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	507458179	7665	0	0
entropy_period_rd_A	507458179	2066	0	0
intr_enable_rd_A	507458179	3092	0	0
prefix_0_rd_A	507458179	2172	0	0
prefix_10_rd_A	507458179	2185	0	0
prefix_1_rd_A	507458179	2296	0	0
prefix_2_rd_A	507458179	2221	0	0
prefix_3_rd_A	507458179	2291	0	0
prefix_4_rd_A	507458179	2250	0	0
prefix_5_rd_A	507458179	2309	0	0
prefix_6_rd_A	507458179	2263	0	0
prefix_7_rd_A	507458179	2315	0	0
prefix_8_rd_A	507458179	2053	0	0
prefix_9_rd_A	507458179	2166	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507458179	7665	0	0
T26	312333	2247	0	0
T65	0	1149	0	0
T66	0	877	0	0
T116	0	3	0	0
T117	0	1	0	0
T122	0	213	0	0
T124	0	156	0	0
T125	0	5	0	0
T126	0	6	0	0
T127	0	146	0	0
T129	177771	0	0	0
T130	89098	0	0	0
T131	916	0	0	0
T132	1015	0	0	0
T133	336715	0	0	0
T134	198219	0	0	0
T135	587636	0	0	0
T136	175376	0	0	0
T137	74541	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507458179	2066	0	0
T26	312333	16	0	0
T89	0	106	0	0
T93	0	6	0	0
T116	0	113	0	0
T126	0	3	0	0
T129	177771	0	0	0
T130	89098	0	0	0
T131	916	0	0	0
T132	1015	0	0	0
T133	336715	0	0	0
T134	198219	0	0	0
T135	587636	0	0	0
T136	175376	0	0	0
T137	74541	0	0	0
T150	0	22	0	0
T151	0	2	0	0
T152	0	10	0	0
T153	0	4	0	0
T154	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507458179	3092	0	0
T26	312333	33	0	0
T116	0	138	0	0
T120	0	13	0	0
T126	0	9	0	0
T129	177771	0	0	0
T130	89098	0	0	0
T131	916	0	0	0
T132	1015	0	0	0
T133	336715	0	0	0
T134	198219	0	0	0
T135	587636	0	0	0
T136	175376	0	0	0
T137	74541	0	0	0
T150	0	11	0	0
T151	0	31	0	0
T152	0	3	0	0
T153	0	6	0	0
T155	0	24	0	0
T156	0	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507458179	2172	0	0
T26	312333	7	0	0
T89	0	48	0	0
T93	0	2	0	0
T116	0	72	0	0
T126	0	3	0	0
T129	177771	0	0	0
T130	89098	0	0	0
T131	916	0	0	0
T132	1015	0	0	0
T133	336715	0	0	0
T134	198219	0	0	0
T135	587636	0	0	0
T136	175376	0	0	0
T137	74541	0	0	0
T150	0	25	0	0
T151	0	12	0	0
T152	0	10	0	0
T153	0	5	0	0
T154	0	3	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507458179	2185	0	0
T26	312333	17	0	0
T89	0	68	0	0
T93	0	11	0	0
T116	0	85	0	0
T126	0	6	0	0
T129	177771	0	0	0
T130	89098	0	0	0
T131	916	0	0	0
T132	1015	0	0	0
T133	336715	0	0	0
T134	198219	0	0	0
T135	587636	0	0	0
T136	175376	0	0	0
T137	74541	0	0	0
T151	0	5	0	0
T152	0	13	0	0
T153	0	3	0	0
T154	0	16	0	0
T157	0	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507458179	2296	0	0
T26	312333	36	0	0
T89	0	78	0	0
T116	0	82	0	0
T126	0	5	0	0
T129	177771	0	0	0
T130	89098	0	0	0
T131	916	0	0	0
T132	1015	0	0	0
T133	336715	0	0	0
T134	198219	0	0	0
T135	587636	0	0	0
T136	175376	0	0	0
T137	74541	0	0	0
T150	0	35	0	0
T151	0	3	0	0
T152	0	10	0	0
T153	0	5	0	0
T154	0	4	0	0
T157	0	20	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507458179	2221	0	0
T26	312333	50	0	0
T89	0	60	0	0
T93	0	9	0	0
T116	0	88	0	0
T126	0	7	0	0
T129	177771	0	0	0
T130	89098	0	0	0
T131	916	0	0	0
T132	1015	0	0	0
T133	336715	0	0	0
T134	198219	0	0	0
T135	587636	0	0	0
T136	175376	0	0	0
T137	74541	0	0	0
T150	0	1	0	0
T151	0	3	0	0
T152	0	6	0	0
T153	0	3	0	0
T154	0	13	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507458179	2291	0	0
T26	312333	44	0	0
T89	0	67	0	0
T116	0	86	0	0
T126	0	5	0	0
T129	177771	0	0	0
T130	89098	0	0	0
T131	916	0	0	0
T132	1015	0	0	0
T133	336715	0	0	0
T134	198219	0	0	0
T135	587636	0	0	0
T136	175376	0	0	0
T137	74541	0	0	0
T150	0	25	0	0
T151	0	1	0	0
T152	0	6	0	0
T153	0	4	0	0
T154	0	8	0	0
T158	0	4	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507458179	2250	0	0
T26	312333	30	0	0
T89	0	53	0	0
T93	0	2	0	0
T116	0	71	0	0
T129	177771	0	0	0
T130	89098	0	0	0
T131	916	0	0	0
T132	1015	0	0	0
T133	336715	0	0	0
T134	198219	0	0	0
T135	587636	0	0	0
T136	175376	0	0	0
T137	74541	0	0	0
T150	0	5	0	0
T151	0	14	0	0
T152	0	9	0	0
T153	0	4	0	0
T154	0	12	0	0
T157	0	21	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507458179	2309	0	0
T26	312333	15	0	0
T89	0	63	0	0
T93	0	7	0	0
T116	0	69	0	0
T126	0	2	0	0
T129	177771	0	0	0
T130	89098	0	0	0
T131	916	0	0	0
T132	1015	0	0	0
T133	336715	0	0	0
T134	198219	0	0	0
T135	587636	0	0	0
T136	175376	0	0	0
T137	74541	0	0	0
T150	0	16	0	0
T151	0	7	0	0
T152	0	12	0	0
T153	0	14	0	0
T154	0	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507458179	2263	0	0
T26	312333	39	0	0
T89	0	66	0	0
T116	0	77	0	0
T126	0	6	0	0
T128	0	6	0	0
T129	177771	0	0	0
T130	89098	0	0	0
T131	916	0	0	0
T132	1015	0	0	0
T133	336715	0	0	0
T134	198219	0	0	0
T135	587636	0	0	0
T136	175376	0	0	0
T137	74541	0	0	0
T150	0	11	0	0
T151	0	4	0	0
T152	0	8	0	0
T153	0	8	0	0
T154	0	14	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507458179	2315	0	0
T26	312333	5	0	0
T89	0	63	0	0
T116	0	98	0	0
T126	0	6	0	0
T129	177771	0	0	0
T130	89098	0	0	0
T131	916	0	0	0
T132	1015	0	0	0
T133	336715	0	0	0
T134	198219	0	0	0
T135	587636	0	0	0
T136	175376	0	0	0
T137	74541	0	0	0
T150	0	66	0	0
T152	0	7	0	0
T153	0	4	0	0
T154	0	16	0	0
T157	0	16	0	0
T159	0	3	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507458179	2053	0	0
T26	312333	44	0	0
T89	0	50	0	0
T93	0	10	0	0
T116	0	78	0	0
T126	0	3	0	0
T129	177771	0	0	0
T130	89098	0	0	0
T131	916	0	0	0
T132	1015	0	0	0
T133	336715	0	0	0
T134	198219	0	0	0
T135	587636	0	0	0
T136	175376	0	0	0
T137	74541	0	0	0
T150	0	22	0	0
T151	0	7	0	0
T152	0	10	0	0
T153	0	10	0	0
T154	0	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507458179	2166	0	0
T26	312333	21	0	0
T89	0	51	0	0
T93	0	7	0	0
T116	0	78	0	0
T129	177771	0	0	0
T130	89098	0	0	0
T131	916	0	0	0
T132	1015	0	0	0
T133	336715	0	0	0
T134	198219	0	0	0
T135	587636	0	0	0
T136	175376	0	0	0
T137	74541	0	0	0
T150	0	30	0	0
T151	0	8	0	0
T152	0	9	0	0
T154	0	11	0	0
T157	0	6	0	0
T160	0	8	0	0