Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	506828957	50950	0	0
RunThenComplete_M	506828957	640336	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	50950	0	0
T1	703044	102	0	0
T2	5257	0	0	0
T3	195091	105	0	0
T4	90568	10	0	0
T7	71155	21	0	0
T8	0	193	0	0
T15	0	57	0	0
T19	107882	35	0	0
T32	120608	62	0	0
T33	837	0	0	0
T34	133423	92	0	0
T35	987	0	0	0
T48	0	23	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	640336	0	0
T1	703044	487	0	0
T2	5257	0	0	0
T3	195091	106	0	0
T4	90568	30	0	0
T7	71155	106	0	0
T8	0	1018	0	0
T15	0	530	0	0
T19	107882	196	0	0
T32	120608	2450	0	0
T33	837	0	0	0
T34	133423	3635	0	0
T35	987	0	0	0
T48	0	113	0	0