Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.76	98.75	96.74	100.00	100.00	97.06	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.76	98.75	96.74	100.00	100.00	97.06	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.76	98.75	96.74	100.00	100.00	97.06	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.82	97.89	92.58	99.89	78.17	95.53	98.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_entropy.u_entropy	97.83	100.00	87.97	100.00	100.00	98.98	100.00
gen_entropy.u_prim_sync_reqack_data	95.83	100.00	83.33			100.00	100.00
intr_fifo_empty	86.94	90.00	77.78			80.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	83.87	94.07	88.60		44.44	92.23	100.00
u_errchk	94.00	95.18	94.59		86.67	93.55	100.00
u_kmac_core	95.80	98.88	92.86	100.00	100.00	91.38	91.67
u_msgfifo	97.43	100.00	95.83	94.52	100.00	94.23	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	99.00	99.25	97.03	100.00		98.72	100.00
u_sha3	96.98	98.85	95.87	100.00	90.48	96.71	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.90	89.96	81.09			88.54	100.00
u_tlul_adapter_msgfifo	80.11	87.12	74.69			77.38	81.25

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		160	158	98.75
ALWAYS	346	0	0
ALWAYS	346	2	2	100.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
ALWAYS	429	9	9	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
ALWAYS	488	6	6	100.00
ALWAYS	501	6	6	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
ALWAYS	561	5	5	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
ALWAYS	651	5	5	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
ALWAYS	687	7	7	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
ALWAYS	765	3	3	100.00
ALWAYS	769	28	28	100.00
ALWAYS	908	3	3	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1034	1	1	100.00
CONT_ASSIGN	1035	1	1	100.00
CONT_ASSIGN	1037	1	1	100.00
CONT_ASSIGN	1040	0	0
ALWAYS	1161	0	0
ALWAYS	1161	2	2	100.00
CONT_ASSIGN	1248	1	1	100.00
CONT_ASSIGN	1391	1	1	100.00
CONT_ASSIGN	1405	1	1	100.00
CONT_ASSIGN	1412	1	1	100.00
CONT_ASSIGN	1417	1	1	100.00
ALWAYS	1423	6	5	83.33
CONT_ASSIGN	1432	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
ALWAYS	1446	4	4	100.00
CONT_ASSIGN	1452	1	1	100.00
ALWAYS	1475	4	4	100.00
ALWAYS	1485	3	3	100.00
CONT_ASSIGN	1496	1	1	100.00
CONT_ASSIGN	1500	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
346	1	1
347	1	1
352	0	1
421	1	1
422	1	1
426	1	1
429	1	1
430	1	1
431	1	1
432	1	1
434	1	1
436	1	1
440	1	1
444	1	1
448	1	1
464	1	1
465	1	1
466	1	1
469	1	1
473	1	1
474	1	1
478	1	1
481	1	1
488	1	1
489	1	1
490	1	1
491	1	1
492	1	1
493	1	1
			MISSING_ELSE
			MISSING_ELSE
501	1	1
502	1	1
503	1	1
504	1	1
505	1	1
506	1	1
			MISSING_ELSE
			MISSING_ELSE
518	1	1
525	1	1
528	1	1
529	1	1
530	1	1
532	1	1
533	1	1
535	1	1
537	1	1
539	1	1
543	1	1
545	1	1
546	1	1
549	1	1
550	1	1
553	1	1
561	1	1
562	1	1
563	1	1
564	1	1
566	1	1
571	1	1
577	1	1
578	1	1
579	1	1
587	1	1
629	1	1
635	1	1
643	1	1
648	1	1
651	1	1
652	1	1
653	1	1
655	1	1
656	1	1
679	1	1
684	1	1
687	1	1
689	1	1
694	1	1
698	1	1
702	1	1
706	1	1
710	1	1
723	1	1
728	1	1
735	1	1
745	1	1
765	3	3
769	1	1
771	1	1
772	1	1
774	1	1
776	1	1
778	1	1
779	1	1
782	1	1
785	1	1
791	1	1
792	1	1
794	1	1
799	1	1
800	1	1
801	1	1
803	1	1
809	1	1
814	1	1
815	1	1
817	1	1
819	1	1
825	1	1
826	1	1
828	1	1
834	1	1
835	1	1
847	1	1
848	1	1
			MISSING_ELSE
908	1	1
909	1	1
911	1	1
916	2	2
992	1	1
994	1	1
1029	1	1
1034	1	1
1035	1	1
1037	1	1
1040		unreachable
1161	1	1
1162	1	1
1248	1	1
1391	1	1
1405	1	1
1412	1	1
1417	1	1
1423	1	1
1424	1	1
1425	1	1
1426	0	1
1427	1	1
1428	1	1
			MISSING_ELSE
1432	1	1
1434	1	1
1446	1	1
1447	1	1
1448	1	1
1449	1	1
			MISSING_ELSE
1452	1	1
1475	1	1
1476	1	1
1477	1	1
1479	1	1
			MISSING_ELSE
1485	1	1
1486	1	1
1489	1	1
1496	1	1
1500	1	1
1502	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	92	89	96.74
Logical	92	89	96.74
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T50,T39

 LINE       539
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T50,T39

 LINE       543
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       550
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T7,T32
1	1	1	Covered	T1,T3,T7

 LINE       563
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T7
1	-	Covered	T1,T2,T3

 LINE       571
 EXPRESSION (reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe)
             -------------1------------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T33,T4

 LINE       629
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

 LINE       635
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T32

 LINE       635
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       635
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       643
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T4

 LINE       643
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T3,T7

 LINE       648
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T7,T32,T34
1	Covered	T1,T2,T3

 LINE       679
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T20,T21,T22
0	0	1	0	Covered	T2,T33,T35
0	1	0	0	Covered	T4,T20,T21
1	0	0	0	Covered	T15,T16,T17

 LINE       723
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T29,T30,T31
0	0	1	0	Covered	T29,T30,T31
0	1	0	0	Covered	T29,T30,T31
1	0	0	0	Covered	T29,T30,T31

 LINE       735
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T29,T30,T31
0	0	0	0	1	0	Covered	T29,T30,T31
0	0	0	1	0	0	Covered	T29,T30,T31
0	0	1	0	0	0	Covered	T29,T30,T31
0	1	0	0	0	0	Covered	T29,T30,T31
1	0	0	0	0	0	Covered	T29,T30,T31

 LINE       776
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       778
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T7,T32

 LINE       792
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T7,T32

 LINE       1029
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T1,T3,T7

 LINE       1162
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T75,T92,T93
1	0	Covered	T1,T2,T3
1	1	Covered	T75,T92,T93

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T75,T92,T93
1	0	Covered	T1,T2,T3
1	1	Covered	T75,T92,T93

 LINE       1434
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T29,T30,T31
0	0	1	0	0	Covered	T12,T13,T14
0	1	0	0	0	Covered	T29,T30,T31
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	71	100.00
Total Bits	6534	6534	100.00
Total Bits 0->1	3267	3267	100.00
Total Bits 1->0	3267	3267	100.00

Ports	71	71	100.00
Port Bits	6534	6534	100.00
Port Bits 0->1	3267	3267	100.00
Port Bits 1->0	3267	3267	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T32,T15,T18	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T32,T15,T18	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T32,T15,T18	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T34,T15	Yes	T4,T34,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T63,T94,T95	Yes	T63,T94,T95	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T75,T92,T93	Yes	T75,T92,T93	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T75,T12,T13	Yes	T75,T12,T13	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T75,T92,T93	Yes	T75,T92,T93	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T75,T12,T13	Yes	T75,T12,T13	OUTPUT
keymgr_key_i.key[0][93:0]	Yes	Yes	T1,T7,T32	Yes	T1,T7,T32	INPUT
keymgr_key_i.key[0][94]	Yes	Yes	T1,T32,T34	Yes	T1,T32,T34	INPUT
keymgr_key_i.key[0][195:95]	Yes	Yes	T1,T7,T32	Yes	T1,T7,T32	INPUT
keymgr_key_i.key[0][196]	Yes	Yes	T1,T32,T34	Yes	T1,T32,T34	INPUT
keymgr_key_i.key[0][255:197]	Yes	Yes	T1,T7,T32	Yes	T1,T7,T32	INPUT
keymgr_key_i.key[1][2:0]	Yes	Yes	T1,T7,T32	Yes	T1,T7,T32	INPUT
keymgr_key_i.key[1][3]	Yes	Yes	T1,T32,T34	Yes	T1,T32,T34	INPUT
keymgr_key_i.key[1][160:4]	Yes	Yes	T1,T7,T32	Yes	T1,T7,T32	INPUT
keymgr_key_i.key[1][162:161]	Yes	Yes	T1,T32,T34	Yes	T1,T32,T34	INPUT
keymgr_key_i.key[1][209:163]	Yes	Yes	T1,T7,T32	Yes	T1,T7,T32	INPUT
keymgr_key_i.key[1][210]	Yes	Yes	T1,T32,T34	Yes	T1,T32,T34	INPUT
keymgr_key_i.key[1][255:211]	Yes	Yes	T1,T7,T32	Yes	T1,T7,T32	INPUT
keymgr_key_i.valid	Yes	Yes	T1,T7,T32	Yes	T1,T7,T32	INPUT
app_i[0].last	Yes	Yes	T1,T7,T4	Yes	T1,T7,T4	INPUT
app_i[0].strb[7:0]	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	INPUT
app_i[0].data[63:0]	Yes	Yes	T1,T7,T4	Yes	T1,T7,T4	INPUT
app_i[0].valid	Yes	Yes	T1,T7,T4	Yes	T1,T7,T4	INPUT
app_i[1].last	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	INPUT
app_i[1].strb[7:0]	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	INPUT
app_i[1].data[63:0]	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	INPUT
app_i[1].valid	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	INPUT
app_i[2].last	Yes	Yes	T1,T8,T15	Yes	T1,T7,T8	INPUT
app_i[2].strb[7:0]	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	INPUT
app_i[2].data[63:0]	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	INPUT
app_i[2].valid	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	INPUT
app_o[0].error	Yes	Yes	T4,T15,T5	Yes	T4,T15,T5	OUTPUT
app_o[0].digest_share1[383:0]	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	OUTPUT
app_o[0].done	Yes	Yes	T1,T7,T4	Yes	T1,T7,T4	OUTPUT
app_o[0].ready	Yes	Yes	T1,T7,T4	Yes	T1,T7,T4	OUTPUT
app_o[1].error	Yes	Yes	T15,T16,T51	Yes	T15,T16,T51	OUTPUT
app_o[1].digest_share1[383:0]	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T1,T8,T15	Yes	T1,T8,T15	OUTPUT
app_o[1].done	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	OUTPUT
app_o[1].ready	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	OUTPUT
app_o[2].error	Yes	Yes	T15,T16,T26	Yes	T15,T16,T26	OUTPUT
app_o[2].digest_share1[383:0]	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	OUTPUT
app_o[2].done	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	OUTPUT
app_o[2].ready	Yes	Yes	T1,T7,T8	Yes	T1,T7,T8	OUTPUT
entropy_o.edn_req	Yes	Yes	T1,T2,T32	Yes	T1,T2,T32	OUTPUT
entropy_i.edn_bus[31:0]	Yes	Yes	T1,T2,T32	Yes	T1,T2,T32	INPUT
entropy_i.edn_fips	Yes	Yes	T1,T2,T32	Yes	T1,T2,T32	INPUT
entropy_i.edn_ack	Yes	Yes	T1,T2,T32	Yes	T1,T2,T32	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T14,T27,T44	Yes	T14,T27,T44	INPUT
intr_kmac_done_o	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
intr_fifo_empty_o	Yes	Yes	T7,T32,T34	Yes	T7,T32,T34	OUTPUT
intr_kmac_err_o	Yes	Yes	T2,T4,T35	Yes	T2,T4,T35	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	817	Covered	T1,T3,T7
KmacIdle	785	Covered	T1,T2,T3
KmacKeyBlock	792	Covered	T1,T7,T32
KmacMsgFeed	782	Covered	T1,T3,T7
KmacPrefix	779	Covered	T1,T7,T32
KmacTerminalError	834	Covered	T12,T13,T14

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	826	Covered	T1,T3,T7
KmacDigest->KmacTerminalError	848	Covered	T45,T65,T66
KmacIdle->KmacMsgFeed	782	Covered	T1,T3,T7
KmacIdle->KmacPrefix	779	Covered	T1,T7,T32
KmacIdle->KmacTerminalError	848	Covered	T29,T30,T31
KmacKeyBlock->KmacMsgFeed	801	Covered	T1,T7,T32
KmacKeyBlock->KmacTerminalError	848	Covered	T13,T44,T28
KmacMsgFeed->KmacDigest	817	Covered	T1,T3,T7
KmacMsgFeed->KmacIdle	814	Covered	T1,T7,T4
KmacMsgFeed->KmacTerminalError	848	Covered	T14,T40,T41
KmacPrefix->KmacKeyBlock	792	Covered	T1,T7,T32
KmacPrefix->KmacMsgFeed	792	Covered	T1,T7,T8
KmacPrefix->KmacTerminalError	848	Covered	T12,T26,T27

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		68	66	97.06
TERNARY	426	2	2	100.00
TERNARY	635	4	4	100.00
TERNARY	643	4	4	100.00
TERNARY	648	2	2	100.00
CASE	434	6	5	83.33
IF	488	3	3	100.00
IF	561	3	3	100.00
IF	651	2	2	100.00
CASE	689	6	6	100.00
IF	765	2	2	100.00
CASE	774	15	15	100.00
IF	847	2	2	100.00
TERNARY	1162	2	2	100.00
IF	1423	4	3	75.00
IF	1446	3	3	100.00
IF	1475	3	3	100.00
IF	1485	2	2	100.00
IF	501	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	426	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	635	(msgfifo_full) ? 
-2-:	635	(msgfifo_empty_negedge) ? 
-3-:	635	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T32
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	643	(app_active) ? 
-2-:	643	((sha3_fsm != StAbsorb)) ? 
-3-:	643	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T4
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	648	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T32,T34

	LineNo.	Expression
-1-:	434	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T3,T7
CmdProcess	Covered	T1,T3,T7
CmdManualRun	Covered	T1,T7,T32
CmdDone	Covered	T1,T3,T7
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	488	if ((!rst_ni))
-2-:	490	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	561	if ((!rst_ni))
-2-:	563	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	651	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	689	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T4,T20,T21
errchecker_err.valid	Covered	T20,T21,T22
sha3_err.valid	Covered	T15,T16,T17
entropy_err.valid	Covered	T2,T33,T35
msgfifo_err.valid	Covered	T29,T30,T31
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	765	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	774	case (kmac_st)
-2-:	776	if ((kmac_cmd == CmdStart))
-3-:	778	if ((CShake == app_sha3_mode))
-4-:	791	if (sha3_block_processed)
-5-:	792	(app_kmac_en) ? 
-6-:	800	if (sha3_block_processed)
-7-:	809	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	815	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	825	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T1,T7,T32
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T3,T7
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T1,T7,T32
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T1,T7,T8
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T1,T7,T32
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T1,T7,T32
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T1,T7,T32
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T1,T7,T4
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T3,T7
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T3,T7
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T3,T7
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T3,T7
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	847	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1162	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1423	if ((!rst_ni))
-2-:	1425	if (alert_recov_operation)
-3-:	1427	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T2,T33,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1446	if ((!rst_ni))
-2-:	1448	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1475	if ((!rst_ni))
-2-:	1477	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1485	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	501	if ((!rst_ni))
-2-:	503	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T7

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	35	100.00	35	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	35	100.00	35	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	506828957	506664057	0	0
CmdSparse_M	506828957	283276	0	0
EnMaskingKnown_A	506828957	506664057	0	0
EntropyReadyLatched_A	506828957	50618	0	0
EntrySizeRegSameToEntrySizePkg_A	654	654	0	0
ErrProcessedLatched_A	506828957	748	0	0
FifoEmpty_A	506828957	506664057	0	0
FpvSecCmErrorCheckFsmCheck_A	506828957	80	0	0
FpvSecCmKeccackFsmCheck_A	506828957	80	0	0
FpvSecCmKeyIndexCountCheck_A	506828957	80	0	0
FpvSecCmKmacAppFsmCheck_A	506828957	80	0	0
FpvSecCmKmacCoreFsmCheck_A	506828957	80	0	0
FpvSecCmKmacFsmCheck_A	506828957	80	0	0
FpvSecCmRegWeOnehotCheck_A	506828957	80	0	0
FpvSecCmRoundCountCheck_A	506828957	80	0	0
FpvSecCmSHA3FsmCheck_A	506828957	80	0	0
FpvSecCmSHA3padFsmCheck_A	506828957	80	0	0
FpvSecCmSentMsgCountCheck_A	506828957	80	0	0
KmacCmd_A	506828957	506664057	0	0
KmacDone_A	506828957	506664057	0	0
KmacErr_A	506828957	506664057	0	0
KmacStKnown_A	506828957	506664057	0	0
NumAlerts2_A	654	654	0	0
NumEntriesRegSameToNumEntriesPkg_A	654	654	0	0
PrefixRegSameToPrefixPkg_A	654	654	0	0
SecretKeyDivideBy32_A	654	654	0	0
Sha3AbsorbedPulse_A	506828957	50945	0	0
TlOAReadyKnown_A	506828957	506664057	0	0
TlODValidKnown_A	506828957	506664057	0	0
g_testassertion.FpvSecCmEntropyFsmCheck_A	506828957	80	0	0
g_testassertion.FpvSecCmHashCountCheck_A	506828957	80	0	0
g_testassertion.FpvSecCmMsgFifoRptrCheck_A	506828957	80	0	0
g_testassertion.FpvSecCmMsgFifoWptrCheck_A	506828957	80	0	0
g_testassertion.FpvSecCmPackerCountCheck_A	506828957	80	0	0
u_state_regs_A	506828957	506664057	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	506664057	0	0
T1	703044	702956	0	0
T2	5257	5164	0	0
T3	195091	194998	0	0
T4	90568	90503	0	0
T7	71155	71100	0	0
T19	107882	107822	0	0
T32	120608	120584	0	0
T33	837	763	0	0
T34	133423	133417	0	0
T35	987	931	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	283276	0	0
T1	703044	584	0	0
T2	5257	24	0	0
T3	195091	339	0	0
T4	90568	11	0	0
T7	71155	101	0	0
T19	107882	257	0	0
T32	120608	431	0	0
T33	837	1	0	0
T34	133423	665	0	0
T35	987	5	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	506664057	0	0
T1	703044	702956	0	0
T2	5257	5164	0	0
T3	195091	194998	0	0
T4	90568	90503	0	0
T7	71155	71100	0	0
T19	107882	107822	0	0
T32	120608	120584	0	0
T33	837	763	0	0
T34	133423	133417	0	0
T35	987	931	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	50618	0	0
T1	703044	102	0	0
T2	5257	20	0	0
T3	195091	104	0	0
T4	90568	10	0	0
T7	71155	21	0	0
T19	107882	35	0	0
T32	120608	62	0	0
T33	837	1	0	0
T34	133423	89	0	0
T35	987	5	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654	654	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	748	0	0
T2	5257	20	0	0
T3	195091	0	0	0
T4	90568	10	0	0
T5	0	19	0	0
T6	0	4	0	0
T7	71155	0	0	0
T19	107882	0	0	0
T32	120608	0	0	0
T33	837	1	0	0
T34	133423	0	0	0
T35	987	5	0	0
T48	164284	0	0	0
T53	0	18	0	0
T96	0	13	0	0
T97	0	5	0	0
T98	0	4	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	506664057	0	0
T1	703044	702956	0	0
T2	5257	5164	0	0
T3	195091	194998	0	0
T4	90568	90503	0	0
T7	71155	71100	0	0
T19	107882	107822	0	0
T32	120608	120584	0	0
T33	837	763	0	0
T34	133423	133417	0	0
T35	987	931	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	506664057	0	0
T1	703044	702956	0	0
T2	5257	5164	0	0
T3	195091	194998	0	0
T4	90568	90503	0	0
T7	71155	71100	0	0
T19	107882	107822	0	0
T32	120608	120584	0	0
T33	837	763	0	0
T34	133423	133417	0	0
T35	987	931	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	506664057	0	0
T1	703044	702956	0	0
T2	5257	5164	0	0
T3	195091	194998	0	0
T4	90568	90503	0	0
T7	71155	71100	0	0
T19	107882	107822	0	0
T32	120608	120584	0	0
T33	837	763	0	0
T34	133423	133417	0	0
T35	987	931	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	506664057	0	0
T1	703044	702956	0	0
T2	5257	5164	0	0
T3	195091	194998	0	0
T4	90568	90503	0	0
T7	71155	71100	0	0
T19	107882	107822	0	0
T32	120608	120584	0	0
T33	837	763	0	0
T34	133423	133417	0	0
T35	987	931	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	506664057	0	0
T1	703044	702956	0	0
T2	5257	5164	0	0
T3	195091	194998	0	0
T4	90568	90503	0	0
T7	71155	71100	0	0
T19	107882	107822	0	0
T32	120608	120584	0	0
T33	837	763	0	0
T34	133423	133417	0	0
T35	987	931	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654	654	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654	654	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654	654	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654	654	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	50945	0	0
T1	703044	102	0	0
T2	5257	0	0	0
T3	195091	105	0	0
T4	90568	10	0	0
T7	71155	21	0	0
T8	0	193	0	0
T15	0	57	0	0
T19	107882	35	0	0
T32	120608	62	0	0
T33	837	0	0	0
T34	133423	92	0	0
T35	987	0	0	0
T48	0	23	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	506664057	0	0
T1	703044	702956	0	0
T2	5257	5164	0	0
T3	195091	194998	0	0
T4	90568	90503	0	0
T7	71155	71100	0	0
T19	107882	107822	0	0
T32	120608	120584	0	0
T33	837	763	0	0
T34	133423	133417	0	0
T35	987	931	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	506664057	0	0
T1	703044	702956	0	0
T2	5257	5164	0	0
T3	195091	194998	0	0
T4	90568	90503	0	0
T7	71155	71100	0	0
T19	107882	107822	0	0
T32	120608	120584	0	0
T33	837	763	0	0
T34	133423	133417	0	0
T35	987	931	0	0

g_testassertion.FpvSecCmEntropyFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

g_testassertion.FpvSecCmHashCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

g_testassertion.FpvSecCmMsgFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

g_testassertion.FpvSecCmMsgFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

g_testassertion.FpvSecCmPackerCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	80	0	0
T6	39496	0	0	0
T29	865433	20	0	0
T30	0	10	0	0
T31	0	10	0	0
T54	700280	0	0	0
T97	27894	0	0	0
T99	0	20	0	0
T100	0	20	0	0
T101	152524	0	0	0
T102	44951	0	0	0
T103	167471	0	0	0
T104	642997	0	0	0
T105	265825	0	0	0
T106	120805	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506828957	506664057	0	0
T1	703044	702956	0	0
T2	5257	5164	0	0
T3	195091	194998	0	0
T4	90568	90503	0	0
T7	71155	71100	0	0
T19	107882	107822	0	0
T32	120608	120584	0	0
T33	837	763	0	0
T34	133423	133417	0	0
T35	987	931	0	0