Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	508367842	4269	0	0
entropy_period_rd_A	508367842	2344	0	0
intr_enable_rd_A	508367842	3555	0	0
prefix_0_rd_A	508367842	2394	0	0
prefix_10_rd_A	508367842	2410	0	0
prefix_1_rd_A	508367842	2433	0	0
prefix_2_rd_A	508367842	2473	0	0
prefix_3_rd_A	508367842	2274	0	0
prefix_4_rd_A	508367842	2491	0	0
prefix_5_rd_A	508367842	2638	0	0
prefix_6_rd_A	508367842	2375	0	0
prefix_7_rd_A	508367842	2474	0	0
prefix_8_rd_A	508367842	2355	0	0
prefix_9_rd_A	508367842	2458	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508367842	4269	0	0
T12	4051	0	0	0
T13	3597	0	0	0
T16	259260	0	0	0
T22	136827	0	0	0
T39	509335	0	0	0
T63	217164	1602	0	0
T64	133883	0	0	0
T91	275042	0	0	0
T94	0	141	0	0
T95	0	3	0	0
T107	0	1	0	0
T110	0	1	0	0
T111	0	2	0	0
T112	0	305	0	0
T122	0	59	0	0
T123	0	2	0	0
T124	0	160	0	0
T126	135848	0	0	0
T127	961748	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508367842	2344	0	0
T76	11676	47	0	0
T81	8250	18	0	0
T110	11198	23	0	0
T111	6258	9	0	0
T123	3969	2	0	0
T136	3675	11	0	0
T137	4995	14	0	0
T138	5923	4	0	0
T139	3015	10	0	0
T140	10409	21	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508367842	3555	0	0
T76	11676	133	0	0
T110	11198	36	0	0
T111	6258	13	0	0
T115	1256	14	0	0
T123	3969	16	0	0
T136	3675	2	0	0
T137	4995	27	0	0
T138	5923	20	0	0
T139	3015	15	0	0
T140	10409	11	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508367842	2394	0	0
T76	11676	44	0	0
T81	8250	26	0	0
T110	11198	18	0	0
T111	6258	8	0	0
T123	3969	6	0	0
T125	22806	91	0	0
T136	3675	9	0	0
T137	4995	15	0	0
T138	5923	38	0	0
T140	10409	44	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508367842	2410	0	0
T76	11676	60	0	0
T81	8250	16	0	0
T110	11198	19	0	0
T111	6258	13	0	0
T123	3969	10	0	0
T125	22806	74	0	0
T136	3675	11	0	0
T137	4995	3	0	0
T138	5923	29	0	0
T140	10409	23	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508367842	2433	0	0
T76	11676	44	0	0
T81	8250	10	0	0
T110	11198	22	0	0
T111	6258	15	0	0
T123	3969	3	0	0
T125	22806	67	0	0
T136	3675	2	0	0
T138	5923	32	0	0
T139	3015	1	0	0
T141	5829	29	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508367842	2473	0	0
T76	11676	35	0	0
T81	8250	26	0	0
T110	11198	22	0	0
T111	6258	8	0	0
T123	3969	6	0	0
T125	22806	69	0	0
T136	3675	6	0	0
T137	4995	28	0	0
T138	5923	8	0	0
T140	10409	8	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508367842	2274	0	0
T76	11676	33	0	0
T81	8250	21	0	0
T110	11198	12	0	0
T111	6258	3	0	0
T123	3969	2	0	0
T136	3675	11	0	0
T137	4995	38	0	0
T138	5923	2	0	0
T139	3015	1	0	0
T140	10409	13	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508367842	2491	0	0
T76	11676	40	0	0
T81	8250	24	0	0
T110	11198	37	0	0
T111	6258	6	0	0
T123	3969	10	0	0
T125	22806	69	0	0
T136	3675	6	0	0
T137	4995	7	0	0
T138	5923	27	0	0
T140	10409	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508367842	2638	0	0
T76	11676	43	0	0
T81	8250	25	0	0
T110	11198	24	0	0
T111	6258	5	0	0
T123	3969	11	0	0
T125	22806	92	0	0
T136	3675	13	0	0
T138	5923	18	0	0
T139	3015	3	0	0
T140	10409	8	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508367842	2375	0	0
T76	11676	28	0	0
T81	8250	16	0	0
T110	11198	28	0	0
T111	6258	4	0	0
T123	3969	5	0	0
T125	22806	79	0	0
T136	3675	17	0	0
T139	3015	1	0	0
T140	10409	3	0	0
T141	5829	29	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508367842	2474	0	0
T76	11676	34	0	0
T81	8250	11	0	0
T110	11198	29	0	0
T111	6258	8	0	0
T123	3969	10	0	0
T136	3675	10	0	0
T137	4995	30	0	0
T138	5923	33	0	0
T139	3015	4	0	0
T140	10409	32	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508367842	2355	0	0
T76	11676	34	0	0
T81	8250	22	0	0
T110	11198	25	0	0
T111	6258	4	0	0
T125	22806	79	0	0
T136	3675	4	0	0
T137	4995	30	0	0
T138	5923	17	0	0
T139	3015	5	0	0
T140	10409	16	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508367842	2458	0	0
T76	11676	47	0	0
T81	8250	22	0	0
T110	11198	20	0	0
T111	6258	9	0	0
T123	3969	2	0	0
T125	22806	87	0	0
T136	3675	11	0	0
T137	4995	8	0	0
T138	5923	32	0	0
T140	10409	26	0	0