Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	640180531	56346	0	0
RunThenComplete_M	640180531	763048	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	56346	0	0
T1	84512	105	0	0
T2	116868	145	0	0
T3	201179	137	0	0
T4	0	16	0	0
T7	14564	3	0	0
T20	311127	29	0	0
T29	448588	197	0	0
T30	4435	3	0	0
T31	9839	3	0	0
T43	159485	73	0	0
T44	1227	0	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	763048	0	0
T1	84512	106	0	0
T2	116868	146	0	0
T3	201179	138	0	0
T4	0	88	0	0
T7	14564	9	0	0
T20	311127	137	0	0
T29	448588	495	0	0
T30	4435	11	0	0
T31	9839	11	0	0
T43	159485	74	0	0
T44	1227	0	0	0