Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.76	98.75	96.74	100.00	100.00	97.06	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.76	98.75	96.74	100.00	100.00	97.06	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.76	98.75	96.74	100.00	100.00	97.06	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.70	97.89	92.55	99.89	77.46	95.53	98.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_entropy.u_entropy	97.83	100.00	87.97	100.00	100.00	98.98	100.00
gen_entropy.u_prim_sync_reqack_data	95.83	100.00	83.33			100.00	100.00
intr_fifo_empty	86.94	90.00	77.78			80.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	83.87	94.07	88.60		44.44	92.23	100.00
u_errchk	92.66	95.18	94.59		80.00	93.55	100.00
u_kmac_core	95.80	98.88	92.86	100.00	100.00	91.38	91.67
u_msgfifo	97.43	100.00	95.83	94.52	100.00	94.23	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.99	99.25	96.97	100.00		98.72	100.00
u_sha3	96.98	98.85	95.87	100.00	90.48	96.71	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.90	89.96	81.09			88.54	100.00
u_tlul_adapter_msgfifo	80.11	87.12	74.69			77.38	81.25

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		160	158	98.75
ALWAYS	346	0	0
ALWAYS	346	2	2	100.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
ALWAYS	429	9	9	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
ALWAYS	488	6	6	100.00
ALWAYS	501	6	6	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
ALWAYS	561	5	5	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
ALWAYS	651	5	5	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
ALWAYS	687	7	7	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
ALWAYS	765	3	3	100.00
ALWAYS	769	28	28	100.00
ALWAYS	908	3	3	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1034	1	1	100.00
CONT_ASSIGN	1035	1	1	100.00
CONT_ASSIGN	1037	1	1	100.00
CONT_ASSIGN	1040	0	0
ALWAYS	1161	0	0
ALWAYS	1161	2	2	100.00
CONT_ASSIGN	1248	1	1	100.00
CONT_ASSIGN	1391	1	1	100.00
CONT_ASSIGN	1405	1	1	100.00
CONT_ASSIGN	1412	1	1	100.00
CONT_ASSIGN	1417	1	1	100.00
ALWAYS	1423	6	5	83.33
CONT_ASSIGN	1432	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
ALWAYS	1446	4	4	100.00
CONT_ASSIGN	1452	1	1	100.00
ALWAYS	1475	4	4	100.00
ALWAYS	1485	3	3	100.00
CONT_ASSIGN	1496	1	1	100.00
CONT_ASSIGN	1500	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	92	89	96.74
Logical	92	89	96.74
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T79,T34

 LINE       539
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T12,T79

 LINE       543
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       550
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T30,T31,T20
1	1	1	Covered	T1,T2,T3

 LINE       563
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T40,T41
1	1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       571
 EXPRESSION (reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe)
             -------------1------------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T44,T45

 LINE       629
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       635
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T9,T10

 LINE       635
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       635
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T4,T9

 LINE       643
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       648
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T30,T50,T11
1	Covered	T1,T2,T3

 LINE       679
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T17,T26,T76
0	0	1	0	Covered	T44,T45,T72
0	1	0	0	Covered	T7,T9,T15
1	0	0	0	Covered	T11,T32,T33

 LINE       723
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T15,T40,T41
0	0	1	0	Covered	T15,T40,T41
0	1	0	0	Covered	T15,T40,T41
1	0	0	0	Covered	T15,T40,T41

 LINE       735
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T15,T40,T41
0	0	0	0	1	0	Covered	T15,T40,T41
0	0	0	1	0	0	Covered	T15,T40,T41
0	0	1	0	0	0	Covered	T15,T40,T41
0	1	0	0	0	0	Covered	T15,T40,T41
1	0	0	0	0	0	Covered	T15,T40,T41

 LINE       776
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       778
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T20

 LINE       792
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T30,T31,T20

 LINE       1029
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1162
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T73,T108
1	0	Covered	T1,T2,T3
1	1	Covered	T46,T73,T108

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T73,T108
1	0	Covered	T1,T2,T3
1	1	Covered	T46,T73,T108

 LINE       1434
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T15,T40,T41
0	0	1	0	0	Covered	T9,T15,T16
0	1	0	0	0	Covered	T15,T40,T41
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	71	100.00
Total Bits	6534	6534	100.00
Total Bits 0->1	3267	3267	100.00
Total Bits 1->0	3267	3267	100.00

Ports	71	71	100.00
Port Bits	6534	6534	100.00
Port Bits 0->1	3267	3267	100.00
Port Bits 1->0	3267	3267	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T9,T15,T16	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T9,T15,T16	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T9,T15,T16	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T43,T31	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T30,T4,T9	Yes	T30,T4,T9	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T43,T30	Yes	T1,T43,T30	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T68,T69,T77	Yes	T68,T69,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T43,T30	Yes	T1,T43,T30	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T46,T73,T108	Yes	T46,T73,T108	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T9,T46,T15	Yes	T9,T46,T15	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T46,T73,T108	Yes	T46,T73,T108	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T9,T46,T15	Yes	T9,T46,T15	OUTPUT
keymgr_key_i.key[0][9:0]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][10]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][16:11]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][17]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][18]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][21:19]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][23:22]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][24]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][25]	Yes	Yes	T20,T29,T9	Yes	T20,T29,T9	INPUT
keymgr_key_i.key[0][36:26]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][37]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][42:38]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][43]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][54:44]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][55]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][63:56]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][64]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][75:65]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][76]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][79:77]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][80]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][88:81]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][89]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][95:90]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][96]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][100:97]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][101]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][104:102]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][105]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][108:106]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][109]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][111:110]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][112]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][114:113]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][115]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][118:116]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][119]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][120]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][121]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][123:122]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][124]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][131:125]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][132]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][139:133]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][140]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][141]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][142]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][148:143]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][149]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][154:150]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][155]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][161:156]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][162]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][175:163]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][176]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][184:177]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][185]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][191:186]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][192]	Yes	Yes	T20,T29,T9	Yes	T20,T29,T9	INPUT
keymgr_key_i.key[0][193]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][194]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][196:195]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][197]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][200:198]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][201]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][203:202]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][204]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][217:205]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][219:218]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][220]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][222:221]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][228:223]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][229]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][232:230]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][233]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][242:234]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][243]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[0][255:244]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][3:0]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][4]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][12:5]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][13]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][14]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][15]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][20:16]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][21]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][24:22]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][25]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][34:26]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][35]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][38:36]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][39]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][40]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][52:41]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][53]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][61:54]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][62]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][66:63]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][67]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][74:68]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][75]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][78:76]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][79]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][80]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][81]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][89:82]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][90]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][91]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][92]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][100:93]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][101]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][108:102]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][109]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][110]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][111]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][113:112]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][114]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][119:115]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][120]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][126:121]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][127]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][131:128]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][132]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][135:133]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][136]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][139:137]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][140]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][145:141]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][146]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][148:147]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][149]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][150]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][151]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][153:152]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][154]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][156:155]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][157]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][161:158]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][162]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][165:163]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][166]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][167]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][171:168]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][172]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][173]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][174]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][175]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][178:176]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][179]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][183:180]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][184]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][197:185]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][200:198]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][207:201]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][208]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][209]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][216:210]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][217]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][219:218]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][220]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][223:221]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][224]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][225]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][230:226]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][231]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][244:232]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][246:245]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][250:247]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][251]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][253:252]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][254]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.key[1][255]	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
keymgr_key_i.valid	Yes	Yes	T20,T29,T4	Yes	T20,T29,T4	INPUT
app_i[0].last	Yes	Yes	T7,T4,T9	Yes	T7,T4,T9	INPUT
app_i[0].strb[7:0]	Yes	Yes	T12,T13,T27	Yes	T12,T13,T27	INPUT
app_i[0].data[63:0]	Yes	Yes	T7,T4,T9	Yes	T7,T4,T9	INPUT
app_i[0].valid	Yes	Yes	T7,T4,T9	Yes	T7,T4,T9	INPUT
app_i[1].last	Yes	Yes	T4,T10,T15	Yes	T4,T10,T15	INPUT
app_i[1].strb[7:0]	Yes	Yes	T12,T13,T27	Yes	T12,T13,T27	INPUT
app_i[1].data[63:0]	Yes	Yes	T4,T10,T15	Yes	T4,T10,T15	INPUT
app_i[1].valid	Yes	Yes	T4,T9,T10	Yes	T4,T9,T10	INPUT
app_i[2].last	Yes	Yes	T4,T9,T15	Yes	T4,T9,T15	INPUT
app_i[2].strb[7:0]	Yes	Yes	T12,T13,T27	Yes	T12,T13,T27	INPUT
app_i[2].data[63:0]	Yes	Yes	T4,T9,T15	Yes	T4,T9,T15	INPUT
app_i[2].valid	Yes	Yes	T4,T9,T15	Yes	T4,T9,T15	INPUT
app_o[0].error	Yes	Yes	T7,T4,T9	Yes	T7,T4,T9	OUTPUT
app_o[0].digest_share1[383:0]	Yes	Yes	T10,T11,T16	Yes	T10,T11,T16	OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
app_o[0].done	Yes	Yes	T7,T4,T9	Yes	T7,T4,T9	OUTPUT
app_o[0].ready	Yes	Yes	T7,T4,T9	Yes	T7,T4,T9	OUTPUT
app_o[1].error	Yes	Yes	T11,T32,T33	Yes	T11,T32,T33	OUTPUT
app_o[1].digest_share1[383:0]	Yes	Yes	T4,T11,T32	Yes	T4,T11,T32	OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T4,T10,T11	Yes	T4,T10,T11	OUTPUT
app_o[1].done	Yes	Yes	T4,T10,T11	Yes	T4,T10,T11	OUTPUT
app_o[1].ready	Yes	Yes	T4,T10,T11	Yes	T4,T10,T11	OUTPUT
app_o[2].error	Yes	Yes	T11,T33,T65	Yes	T11,T33,T65	OUTPUT
app_o[2].digest_share1[383:0]	Yes	Yes	T4,T9,T11	Yes	T4,T9,T11	OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T4,T9,T11	Yes	T4,T9,T11	OUTPUT
app_o[2].done	Yes	Yes	T4,T9,T11	Yes	T4,T9,T11	OUTPUT
app_o[2].ready	Yes	Yes	T4,T9,T11	Yes	T4,T9,T11	OUTPUT
entropy_o.edn_req	Yes	Yes	T2,T30,T31	Yes	T2,T30,T31	OUTPUT
entropy_i.edn_bus[31:0]	Yes	Yes	T30,T9,T51	Yes	T2,T44,T9	INPUT
entropy_i.edn_fips	Yes	Yes	T2,T30,T31	Yes	T2,T30,T49	INPUT
entropy_i.edn_ack	Yes	Yes	T2,T30,T31	Yes	T2,T30,T31	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T16,T42,T37	Yes	T16,T42,T37	INPUT
intr_kmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T30,T50,T11	Yes	T30,T50,T11	OUTPUT
intr_kmac_err_o	Yes	Yes	T7,T44,T45	Yes	T7,T44,T45	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	817	Covered	T1,T2,T3
KmacIdle	785	Covered	T1,T2,T3
KmacKeyBlock	792	Covered	T30,T31,T20
KmacMsgFeed	782	Covered	T1,T2,T3
KmacPrefix	779	Covered	T30,T31,T20
KmacTerminalError	834	Covered	T9,T15,T16

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	826	Covered	T1,T2,T3
KmacDigest->KmacTerminalError	848	Covered	T62,T63,T64
KmacIdle->KmacMsgFeed	782	Covered	T1,T2,T3
KmacIdle->KmacPrefix	779	Covered	T30,T31,T20
KmacIdle->KmacTerminalError	848	Covered	T15,T40,T41
KmacKeyBlock->KmacMsgFeed	801	Covered	T30,T31,T20
KmacKeyBlock->KmacTerminalError	848	Covered	T39,T58,T92
KmacMsgFeed->KmacDigest	817	Covered	T1,T2,T3
KmacMsgFeed->KmacIdle	814	Covered	T7,T4,T9
KmacMsgFeed->KmacTerminalError	848	Covered	T9,T42,T37
KmacPrefix->KmacKeyBlock	792	Covered	T30,T31,T20
KmacPrefix->KmacMsgFeed	792	Covered	T4,T9,T10
KmacPrefix->KmacTerminalError	848	Covered	T16,T95,T54

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		68	66	97.06
TERNARY	426	2	2	100.00
TERNARY	635	4	4	100.00
TERNARY	643	4	4	100.00
TERNARY	648	2	2	100.00
CASE	434	6	5	83.33
IF	488	3	3	100.00
IF	561	3	3	100.00
IF	651	2	2	100.00
CASE	689	6	6	100.00
IF	765	2	2	100.00
CASE	774	15	15	100.00
IF	847	2	2	100.00
TERNARY	1162	2	2	100.00
IF	1423	4	3	75.00
IF	1446	3	3	100.00
IF	1475	3	3	100.00
IF	1485	2	2	100.00
IF	501	3	3	100.00

426          assign sw_cmd = (cmd_update) ? cmd_q : CmdNone;
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

635          assign msgfifo_full_seen_d =
                                         
636              msgfifo_full          ? 1'b 1 :
                                       -1-  
                                       ==>  
637              msgfifo_empty_negedge ? 1'b 0 :
                                       -2-  
                                       ==>  
638              msgfifo2kmac_process  ? 1'b 0 : msgfifo_full_seen_q;
                                       -3-  
                                       ==>  
                                       ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T30,T9,T10
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

643          assign msgfifo_empty_gate =
                                        
644              app_active                     ? 1'b 1 :
                                                -1-  
                                                ==>  
645              sha3_fsm != sha3_pkg::StAbsorb ? 1'b 1 :
                                                -2-  
                                                ==>  
646              msgfifo2kmac_process           ? 1'b 1 : ~msgfifo_full_seen_q;
                                                -3-  
                                                ==>  
                                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T4,T9
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

648          assign status_msgfifo_empty = msgfifo_empty_gate ? 1'b 0 : msgfifo_empty;
                                                              -1-  
                                                              ==>  
                                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T30,T50,T11

434            unique case (kmac_cmd)
                      -1-  
435              CmdStart: begin
436                sha3_start = 1'b 1;
                   ==>
437              end
438        
439              CmdProcess: begin
440                reg2msgfifo_process = 1'b 1;
                   ==>
441              end
442        
443              CmdManualRun: begin
444                sha3_run = 1'b 1;
                   ==>
445              end
446        
447              CmdDone: begin
448                sha3_done_d = prim_mubi_pkg::MuBi4True;
                   ==>
449              end
450        
451              CmdNone: begin
                 ==>
452                // inactive state
453              end
454        
455              default: begin
                 ==>

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T3
CmdManualRun	Covered	T20,T9,T10
CmdDone	Covered	T1,T2,T3
CmdNone	Covered	T1,T2,T3
default	Not Covered

488            if (!rst_ni) begin
               -1-  
489              sw_key_data_reg[0] <= '0;
                 ==>
490            end else if (engine_stable) begin
                        -2-  
491              for (int j = 0 ; j < MaxKeyLen/32 ; j++) begin
                 ==>
492                if (reg2hw.key_share0[j].qe) begin
493                  sw_key_data_reg[0][32*j+:32] <= reg2hw.key_share0[j].q;
494                end
495              end // for j
496            end // else if engine_stable
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

561            if (!rst_ni) begin
               -1-  
562              idle_o <= prim_mubi_pkg::MuBi4True;
                 ==>
563            end else if ((sha3_fsm == sha3_pkg::StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)) begin
                        -2-                                           
564              idle_o <= prim_mubi_pkg::MuBi4True;
                 ==>
565            end else begin
566              idle_o <= prim_mubi_pkg::MuBi4False;
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

651            if (!rst_ni) begin
               -1-  
652              msgfifo_empty_q     <= 1'b 0;
                 ==>
653              msgfifo_full_seen_q <= 1'b 0;
654            end else begin
655              msgfifo_empty_q     <= msgfifo_empty;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

689            priority case (1'b 1)
                        -1-  
690              // app_err has the highest priority. If SW issues an incorrect command
691              // while app is in active state, the error from AppIntf is passed
692              // through.
693              app_err.valid: begin
694                hw2reg.err_code.d = {app_err.code, app_err.info};
                   ==>
695              end
696        
697              errchecker_err.valid: begin
698                hw2reg.err_code.d = {errchecker_err.code , errchecker_err.info};
                   ==>
699              end
700        
701              sha3_err.valid: begin
702                hw2reg.err_code.d = {sha3_err.code , sha3_err.info};
                   ==>
703              end
704        
705              entropy_err.valid: begin
706                hw2reg.err_code.d = {entropy_err.code, entropy_err.info};
                   ==>
707              end
708        
709              msgfifo_err.valid: begin
710                hw2reg.err_code.d = {msgfifo_err.code, msgfifo_err.info};
                   ==>
711              end
712        
713              default: begin
714                hw2reg.err_code.d = '0;
                   ==>

Branches:

-1-	Status	Tests
app_err.valid	Covered	T7,T9,T15
errchecker_err.valid	Covered	T17,T26,T76
sha3_err.valid	Covered	T11,T32,T33
entropy_err.valid	Covered	T44,T45,T72
msgfifo_err.valid	Covered	T15,T40,T41
default	Covered	T1,T2,T3

765          `PRIM_FLOP_SPARSE_FSM(u_state_regs, kmac_st_d, kmac_st, kmac_st_e, KmacIdle)
             -1-                                                                            
             ==>                                                                            
             ==>                                                                            

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

774            unique case (kmac_st)
                      -1-  
775              KmacIdle: begin
776                if (kmac_cmd == CmdStart) begin
                   -2-  
777                  // If cSHAKE turned on
778                  if (sha3_pkg::CShake == app_sha3_mode) begin
                     -3-  
779                    kmac_st_d = KmacPrefix;
                       ==>
780                  end else begin
781                    // Jump to Msg feed directly
782                    kmac_st_d = KmacMsgFeed;
                       ==>
783                  end
784                end else begin
785                  kmac_st_d = KmacIdle;
                     ==>
786                end
787              end
788        
789              KmacPrefix: begin
790                // Wait until SHA3 processes one block
791                if (sha3_block_processed) begin
                   -4-  
792                  kmac_st_d = (app_kmac_en) ? KmacKeyBlock : KmacMsgFeed ;
                                               -5-  
                                               ==>  
                                               ==>  
793                end else begin
794                  kmac_st_d = KmacPrefix;
                     ==>
795                end
796              end
797        
798              KmacKeyBlock: begin
799                entropy_in_keyblock = 1'b 1;
800                if (sha3_block_processed) begin
                   -6-  
801                  kmac_st_d = KmacMsgFeed;
                     ==>
802                end else begin
803                  kmac_st_d = KmacKeyBlock;
                     ==>
804                end
805              end
806        
807              KmacMsgFeed: begin
808                // If absorbed, move to Digest
809                if (prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) &&
                   -7-  
810                  prim_mubi_pkg::mubi4_test_true_strict(sha3_done)) begin
811                  // absorbed and done can be asserted at a cycle if Applications have
812                  // requested the hash operation. kmac_app FSM issues CmdDone command
813                  // if it receives absorbed signal.
814                  kmac_st_d = KmacIdle;
                     ==>
815                end else if (prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) &&
                            -8-  
816                  prim_mubi_pkg::mubi4_test_false_loose(sha3_done)) begin
817                  kmac_st_d = KmacDigest;
                     ==>
818                end else begin
819                  kmac_st_d = KmacMsgFeed;
                     ==>
820                end
821              end
822        
823              KmacDigest: begin
824                // SW can manually run it, wait till done
825                if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done)) begin
                   -9-  
826                  kmac_st_d = KmacIdle;
                     ==>
827                end else begin
828                  kmac_st_d = KmacDigest;
                     ==>
829                end
830              end
831        
832              KmacTerminalError: begin
833                //this state is terminal
834                kmac_st_d = KmacTerminalError;
                   ==>
835                kmac_state_error = 1'b 1;
836              end
837        
838              default: begin
839                kmac_st_d = KmacTerminalError;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T30,T31,T20
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T30,T31,T20
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T4,T9,T10
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T30,T31,T20
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T30,T31,T20
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T30,T31,T20
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T7,T4,T9
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T9,T15,T16
default	-	-	-	-	-	-	-	-	Covered	T15,T40,T41

847            if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0])) begin
               -1-  
848              kmac_st_d = KmacTerminalError;
                 ==>
849            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T9,T15,T16
0	Covered	T1,T2,T3

1162             reg_state_tl[i] = reg_state_valid ? reg_state[i] : 'b0;
                                                   -1-  
                                                   ==>  
                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

1423           if (!rst_ni) begin
               -1-  
1424             status_alert_recov_ctrl_update_err <= 1'b 0;
                 ==>
1425           end else if (alert_recov_operation) begin
                        -2-  
1426             status_alert_recov_ctrl_update_err <= 1'b 1;
                 ==>
1427           end else if (err_processed) begin
                        -3-  
1428             status_alert_recov_ctrl_update_err <= 1'b 0;
                 ==>
1429           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T7,T44,T45
0	0	0	Covered	T1,T2,T3

1446           if (!rst_ni) begin
               -1-  
1447             status_alert_fatal_fault <= 1'b 0;
                 ==>
1448           end else if (alert_fatal) begin
                        -2-  
1449             status_alert_fatal_fault <= 1'b 1;
                 ==>
1450           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T9,T15,T16
0	0	Covered	T1,T2,T3

1475           if (!rst_ni) begin
               -1-  
1476             alerts_q[1] <= 1'b0;
                 ==>
1477           end else if (alerts[1]) begin
                        -2-  
1478             // fatal alerts cannot be cleared
1479             alerts_q[1] <= 1'b1;
                 ==>
1480           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T9,T15,T16
0	0	Covered	T1,T2,T3

1485           if (!rst_ni) begin
               -1-  
1486             alerts_q[0] <= 1'b0;
                 ==>
1487           end else begin
1488             // recoverable alerts can be cleared so just latch the value
1489             alerts_q[0] <= alerts[0];
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

501              if (!rst_ni) begin
                 -1-  
502                sw_key_data_reg[1] <= '0;
                   ==>
503              end else if (engine_stable) begin
                          -2-  
504                for (int j = 0 ; j < MaxKeyLen/32 ; j++) begin
                   ==>
505                  if (reg2hw.key_share1[j].qe) begin
506                    sw_key_data_reg[1][32*j+:32] <= reg2hw.key_share1[j].q;
507                  end
508                end // for j
509              end // else if engine_stable
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	35	100.00	35	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	35	100.00	35	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	640180531	640001293	0	0
CmdSparse_M	640180531	317544	0	0
EnMaskingKnown_A	640180531	640001293	0	0
EntropyReadyLatched_A	640180531	55952	0	0
EntrySizeRegSameToEntrySizePkg_A	665	665	0	0
ErrProcessedLatched_A	640180531	761	0	0
FifoEmpty_A	640180531	640001293	0	0
FpvSecCmErrorCheckFsmCheck_A	640180531	90	0	0
FpvSecCmKeccackFsmCheck_A	640180531	90	0	0
FpvSecCmKeyIndexCountCheck_A	640180531	90	0	0
FpvSecCmKmacAppFsmCheck_A	640180531	90	0	0
FpvSecCmKmacCoreFsmCheck_A	640180531	90	0	0
FpvSecCmKmacFsmCheck_A	640180531	90	0	0
FpvSecCmRegWeOnehotCheck_A	640180531	90	0	0
FpvSecCmRoundCountCheck_A	640180531	90	0	0
FpvSecCmSHA3FsmCheck_A	640180531	90	0	0
FpvSecCmSHA3padFsmCheck_A	640180531	90	0	0
FpvSecCmSentMsgCountCheck_A	640180531	90	0	0
KmacCmd_A	640180531	640001293	0	0
KmacDone_A	640180531	640001293	0	0
KmacErr_A	640180531	640001293	0	0
KmacStKnown_A	640180531	640001293	0	0
NumAlerts2_A	665	665	0	0
NumEntriesRegSameToNumEntriesPkg_A	665	665	0	0
PrefixRegSameToPrefixPkg_A	665	665	0	0
SecretKeyDivideBy32_A	665	665	0	0
Sha3AbsorbedPulse_A	640180531	56336	0	0
TlOAReadyKnown_A	640180531	640001293	0	0
TlODValidKnown_A	640180531	640001293	0	0
g_testassertion.FpvSecCmEntropyFsmCheck_A	640180531	90	0	0
g_testassertion.FpvSecCmHashCountCheck_A	640180531	90	0	0
g_testassertion.FpvSecCmMsgFifoRptrCheck_A	640180531	90	0	0
g_testassertion.FpvSecCmMsgFifoWptrCheck_A	640180531	90	0	0
g_testassertion.FpvSecCmPackerCountCheck_A	640180531	90	0	0
u_state_regs_A	640180531	640001293	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	317544	0	0
T1	84512	335	0	0
T2	116868	466	0	0
T3	201179	441	0	0
T7	14564	4	0	0
T20	311127	204	0	0
T29	448588	624	0	0
T30	4435	10	0	0
T31	9839	9	0	0
T43	159485	237	0	0
T44	1227	2	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	55952	0	0
T1	84512	103	0	0
T2	116868	140	0	0
T3	201179	132	0	0
T7	14564	3	0	0
T20	311127	29	0	0
T29	448588	195	0	0
T30	4435	3	0	0
T31	9839	3	0	0
T43	159485	72	0	0
T44	1227	2	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	761	0	0
T4	98565	0	0	0
T7	14564	3	0	0
T8	0	7	0	0
T9	68458	0	0	0
T10	225064	0	0	0
T14	0	13	0	0
T44	1227	2	0	0
T45	1030	2	0	0
T46	1219	0	0	0
T47	30194	0	0	0
T48	56730	0	0	0
T49	9834	0	0	0
T72	0	4	0	0
T86	0	18	0	0
T109	0	20	0	0
T110	0	8	0	0
T111	0	5	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665	665	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	56336	0	0
T1	84512	105	0	0
T2	116868	145	0	0
T3	201179	137	0	0
T4	0	16	0	0
T7	14564	3	0	0
T20	311127	29	0	0
T29	448588	197	0	0
T30	4435	3	0	0
T31	9839	3	0	0
T43	159485	73	0	0
T44	1227	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0

g_testassertion.FpvSecCmEntropyFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

g_testassertion.FpvSecCmHashCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

g_testassertion.FpvSecCmMsgFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

g_testassertion.FpvSecCmMsgFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

g_testassertion.FpvSecCmPackerCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	90	0	0
T8	66814	0	0	0
T11	890060	0	0	0
T12	550254	0	0	0
T15	745929	20	0	0
T16	48958	0	0	0
T23	214821	0	0	0
T32	296376	0	0	0
T40	0	20	0	0
T41	0	20	0	0
T72	1157	0	0	0
T73	1247	0	0	0
T74	341080	0	0	0
T112	0	10	0	0
T113	0	20	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	640180531	640001293	0	0
T1	84512	84419	0	0
T2	116868	116792	0	0
T3	201179	201095	0	0
T7	14564	14467	0	0
T20	311127	311045	0	0
T29	448588	448489	0	0
T30	4435	4372	0	0
T31	9839	9765	0	0
T43	159485	159405	0	0
T44	1227	1146	0	0