Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	641653231	14147	0	0
entropy_period_rd_A	641653231	1860	0	0
intr_enable_rd_A	641653231	2528	0	0
prefix_0_rd_A	641653231	2042	0	0
prefix_10_rd_A	641653231	1967	0	0
prefix_1_rd_A	641653231	1901	0	0
prefix_2_rd_A	641653231	1915	0	0
prefix_3_rd_A	641653231	1890	0	0
prefix_4_rd_A	641653231	2012	0	0
prefix_5_rd_A	641653231	1932	0	0
prefix_6_rd_A	641653231	1945	0	0
prefix_7_rd_A	641653231	1967	0	0
prefix_8_rd_A	641653231	1926	0	0
prefix_9_rd_A	641653231	1844	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641653231	14147	0	0
T68	481939	5957	0	0
T69	200344	2281	0	0
T77	0	2505	0	0
T80	990444	0	0	0
T83	102240	0	0	0
T113	714124	0	0	0
T115	0	2	0	0
T116	0	2	0	0
T117	0	1	0	0
T121	0	205	0	0
T122	0	3	0	0
T123	0	179	0	0
T124	0	5	0	0
T126	131855	0	0	0
T127	85318	0	0	0
T128	2567	0	0	0
T129	241816	0	0	0
T130	1006	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641653231	1860	0	0
T96	2022	8	0	0
T98	5118	29	0	0
T105	11819	117	0	0
T115	11476	82	0	0
T116	25387	55	0	0
T119	2606	5	0	0
T146	48581	459	0	0
T147	3586	9	0	0
T148	6854	29	0	0
T149	1692	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641653231	2528	0	0
T96	2022	7	0	0
T98	5118	22	0	0
T105	11819	106	0	0
T115	11476	84	0	0
T116	25387	77	0	0
T118	987	5	0	0
T119	2606	9	0	0
T146	48581	459	0	0
T147	3586	4	0	0
T150	6220	2	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641653231	2042	0	0
T96	2022	8	0	0
T98	5118	29	0	0
T105	11819	55	0	0
T115	11476	60	0	0
T116	25387	71	0	0
T119	2606	3	0	0
T146	48581	453	0	0
T147	3586	5	0	0
T148	6854	13	0	0
T150	6220	28	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641653231	1967	0	0
T96	2022	3	0	0
T98	5118	20	0	0
T105	11819	49	0	0
T115	11476	36	0	0
T116	25387	50	0	0
T119	2606	7	0	0
T146	48581	433	0	0
T147	3586	6	0	0
T148	6854	6	0	0
T150	6220	10	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641653231	1901	0	0
T96	2022	8	0	0
T98	5118	15	0	0
T105	11819	53	0	0
T115	11476	49	0	0
T116	25387	33	0	0
T119	2606	2	0	0
T146	48581	442	0	0
T147	3586	7	0	0
T148	6854	23	0	0
T150	6220	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641653231	1915	0	0
T96	2022	4	0	0
T98	5118	19	0	0
T105	11819	43	0	0
T115	11476	51	0	0
T116	25387	53	0	0
T119	2606	6	0	0
T146	48581	467	0	0
T147	3586	8	0	0
T148	6854	8	0	0
T150	6220	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641653231	1890	0	0
T96	2022	7	0	0
T98	5118	15	0	0
T105	11819	50	0	0
T115	11476	44	0	0
T116	25387	25	0	0
T119	2606	7	0	0
T146	48581	450	0	0
T147	3586	12	0	0
T148	6854	38	0	0
T150	6220	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641653231	2012	0	0
T96	2022	8	0	0
T98	5118	20	0	0
T105	11819	63	0	0
T115	11476	38	0	0
T116	25387	43	0	0
T119	2606	7	0	0
T146	48581	447	0	0
T147	3586	5	0	0
T148	6854	22	0	0
T150	6220	12	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641653231	1932	0	0
T96	2022	9	0	0
T98	5118	22	0	0
T105	11819	49	0	0
T115	11476	39	0	0
T116	25387	25	0	0
T119	2606	4	0	0
T146	48581	450	0	0
T147	3586	13	0	0
T148	6854	33	0	0
T150	6220	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641653231	1945	0	0
T98	5118	17	0	0
T105	11819	47	0	0
T115	11476	21	0	0
T116	25387	39	0	0
T119	2606	6	0	0
T146	48581	433	0	0
T147	3586	5	0	0
T148	6854	13	0	0
T149	1692	4	0	0
T150	6220	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641653231	1967	0	0
T96	2022	3	0	0
T98	5118	19	0	0
T105	11819	61	0	0
T115	11476	37	0	0
T116	25387	31	0	0
T119	2606	3	0	0
T146	48581	443	0	0
T147	3586	5	0	0
T148	6854	18	0	0
T149	1692	3	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641653231	1926	0	0
T96	2022	4	0	0
T98	5118	24	0	0
T105	11819	59	0	0
T115	11476	56	0	0
T116	25387	45	0	0
T119	2606	9	0	0
T146	48581	436	0	0
T147	3586	11	0	0
T148	6854	25	0	0
T150	6220	2	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641653231	1844	0	0
T96	2022	7	0	0
T98	5118	29	0	0
T105	11819	68	0	0
T115	11476	41	0	0
T116	25387	27	0	0
T119	2606	3	0	0
T146	48581	440	0	0
T147	3586	1	0	0
T148	6854	31	0	0
T150	6220	4	0	0