Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
166827 |
1 |
|
|
T4 |
602 |
|
T12 |
43 |
|
T5 |
542 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
83474 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
63423 |
1 |
|
|
T4 |
592 |
|
T12 |
42 |
|
T5 |
534 |
seven_bytes |
2941 |
1 |
|
|
T13 |
22 |
|
T15 |
18 |
|
T16 |
33 |
six_bytes |
2840 |
1 |
|
|
T13 |
14 |
|
T15 |
20 |
|
T16 |
21 |
five_bytes |
2859 |
1 |
|
|
T13 |
19 |
|
T15 |
16 |
|
T16 |
36 |
four_bytes |
2820 |
1 |
|
|
T13 |
12 |
|
T15 |
20 |
|
T16 |
29 |
three_bytes |
2822 |
1 |
|
|
T13 |
18 |
|
T15 |
20 |
|
T16 |
35 |
two_bytes |
2798 |
1 |
|
|
T13 |
24 |
|
T15 |
27 |
|
T16 |
27 |
one_byte |
2850 |
1 |
|
|
T13 |
22 |
|
T15 |
17 |
|
T16 |
26 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163537 |
1 |
|
|
T4 |
582 |
|
T12 |
41 |
|
T5 |
526 |
auto[1] |
3290 |
1 |
|
|
T4 |
20 |
|
T12 |
2 |
|
T5 |
16 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
166827 |
1 |
|
|
T4 |
602 |
|
T12 |
43 |
|
T5 |
542 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
166815 |
1 |
|
|
T4 |
602 |
|
T12 |
43 |
|
T5 |
542 |
auto[1] |
12 |
1 |
|
|
T6 |
1 |
|
T80 |
1 |
|
T180 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1154 |
1 |
|
|
T4 |
10 |
|
T12 |
1 |
|
T5 |
8 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3290 |
1 |
|
|
T4 |
20 |
|
T12 |
2 |
|
T5 |
16 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170020 |
1 |
|
|
T9 |
4 |
|
T10 |
2 |
|
T4 |
693 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
86801 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
62644 |
1 |
|
|
T9 |
4 |
|
T10 |
2 |
|
T4 |
683 |
seven_bytes |
2897 |
1 |
|
|
T13 |
2 |
|
T15 |
35 |
|
T128 |
1 |
six_bytes |
2873 |
1 |
|
|
T13 |
5 |
|
T15 |
30 |
|
T16 |
32 |
five_bytes |
2983 |
1 |
|
|
T13 |
4 |
|
T15 |
30 |
|
T16 |
29 |
four_bytes |
2952 |
1 |
|
|
T13 |
6 |
|
T15 |
31 |
|
T16 |
25 |
three_bytes |
2936 |
1 |
|
|
T13 |
7 |
|
T15 |
40 |
|
T16 |
24 |
two_bytes |
2976 |
1 |
|
|
T13 |
10 |
|
T15 |
40 |
|
T16 |
21 |
one_byte |
2958 |
1 |
|
|
T13 |
6 |
|
T15 |
50 |
|
T16 |
21 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
166671 |
1 |
|
|
T9 |
4 |
|
T10 |
2 |
|
T4 |
673 |
auto[1] |
3349 |
1 |
|
|
T4 |
20 |
|
T12 |
6 |
|
T5 |
14 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170020 |
1 |
|
|
T9 |
4 |
|
T10 |
2 |
|
T4 |
693 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170010 |
1 |
|
|
T9 |
4 |
|
T10 |
2 |
|
T4 |
693 |
auto[1] |
10 |
1 |
|
|
T83 |
1 |
|
T148 |
1 |
|
T95 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1184 |
1 |
|
|
T4 |
10 |
|
T12 |
3 |
|
T5 |
7 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3349 |
1 |
|
|
T4 |
20 |
|
T12 |
6 |
|
T5 |
14 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
336792 |
1 |
|
|
T4 |
683 |
|
T17 |
58 |
|
T12 |
105 |
auto[1] |
526 |
1 |
|
|
T4 |
16 |
|
T5 |
23 |
|
T6 |
85 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
170423 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
126134 |
1 |
|
|
T4 |
683 |
|
T17 |
58 |
|
T12 |
104 |
seven_bytes |
5816 |
1 |
|
|
T13 |
16 |
|
T15 |
50 |
|
T128 |
12 |
six_bytes |
5829 |
1 |
|
|
T13 |
29 |
|
T15 |
47 |
|
T128 |
18 |
five_bytes |
5814 |
1 |
|
|
T13 |
16 |
|
T15 |
48 |
|
T128 |
12 |
four_bytes |
5930 |
1 |
|
|
T13 |
22 |
|
T15 |
43 |
|
T128 |
11 |
three_bytes |
5811 |
1 |
|
|
T13 |
23 |
|
T15 |
41 |
|
T128 |
12 |
two_bytes |
5787 |
1 |
|
|
T13 |
28 |
|
T15 |
48 |
|
T128 |
12 |
one_byte |
5774 |
1 |
|
|
T13 |
13 |
|
T15 |
46 |
|
T128 |
11 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
330748 |
1 |
|
|
T4 |
667 |
|
T17 |
58 |
|
T12 |
103 |
auto[1] |
6570 |
1 |
|
|
T4 |
32 |
|
T12 |
2 |
|
T5 |
46 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
337318 |
1 |
|
|
T4 |
699 |
|
T17 |
58 |
|
T12 |
105 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
337294 |
1 |
|
|
T4 |
699 |
|
T17 |
58 |
|
T12 |
105 |
auto[1] |
24 |
1 |
|
|
T6 |
3 |
|
T181 |
1 |
|
T182 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2328 |
1 |
|
|
T4 |
16 |
|
T12 |
1 |
|
T5 |
23 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6570 |
1 |
|
|
T4 |
32 |
|
T12 |
2 |
|
T5 |
46 |