Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49880917	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

49274179

1

T1

321

T2

442

T3

226

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54059684	1			T1	233		T2	391		T3	62
values[0x0]	21838284	1			T1	175		T2	192		T3	110
values[0x1]	23257128	1			T1	162		T2	187		T3	124

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38419336	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

60735760

1

T1

385

T2

516

T3

238

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	312099	1			T2	2		T11	56		T53	1
valid_sources[0x01]	589059	1			T2	5		T11	38		T55	2
valid_sources[0x02]	323391	1			T2	5		T11	14		T54	1
valid_sources[0x03]	315355	1			T2	4		T11	22		T53	1
valid_sources[0x04]	312419	1			T2	5		T11	71		T53	2
valid_sources[0x05]	321441	1			T2	8		T11	10		T55	3
valid_sources[0x06]	315592	1			T2	6		T11	50		T53	7
valid_sources[0x07]	358142	1			T2	2		T11	29		T53	2
valid_sources[0x08]	316636	1			T2	3		T11	54		T53	6
valid_sources[0x09]	315517	1			T2	6		T11	7		T53	1
valid_sources[0x0a]	313949	1			T2	2		T11	30		T53	5
valid_sources[0x0b]	315629	1			T2	6		T3	2		T11	33
valid_sources[0x0c]	313616	1			T2	3		T11	14		T53	2
valid_sources[0x0d]	358434	1			T2	3		T11	30		T53	2
valid_sources[0x0e]	317168	1			T2	1		T11	18		T53	1
valid_sources[0x0f]	316545	1			T2	4		T11	32		T53	4
valid_sources[0x10]	623556	1			T2	5		T11	23		T55	2
valid_sources[0x11]	314142	1			T11	72		T53	4		T55	4
valid_sources[0x12]	394215	1			T2	6		T11	88		T53	3
valid_sources[0x13]	428665	1			T2	5		T3	15		T11	40
valid_sources[0x14]	317223	1			T2	2		T11	41		T53	2
valid_sources[0x15]	377389	1			T2	4		T11	41		T55	4
valid_sources[0x16]	315558	1			T2	5		T3	6		T11	19
valid_sources[0x17]	312383	1			T2	8		T3	6		T11	53
valid_sources[0x18]	317166	1			T2	2		T11	50		T55	1
valid_sources[0x19]	315518	1			T2	3		T11	28		T53	1
valid_sources[0x1a]	314148	1			T2	4		T11	23		T53	3
valid_sources[0x1b]	323446	1			T2	2		T11	27		T53	8
valid_sources[0x1c]	380278	1			T3	4		T11	31		T53	1
valid_sources[0x1d]	316547	1			T2	6		T11	74		T53	2
valid_sources[0x1e]	552988	1			T2	3		T11	65		T55	4
valid_sources[0x1f]	314675	1			T2	2		T3	1		T11	8
valid_sources[0x20]	315627	1			T2	3		T3	10		T11	51
valid_sources[0x21]	314886	1			T2	4		T11	60		T53	4
valid_sources[0x22]	312583	1			T2	2		T11	90		T53	1
valid_sources[0x23]	392730	1			T3	7		T11	49		T53	3
valid_sources[0x24]	312805	1			T2	2		T11	33		T53	2
valid_sources[0x25]	315014	1			T2	3		T11	17		T53	2
valid_sources[0x26]	316156	1			T2	8		T11	7		T53	1
valid_sources[0x27]	312362	1			T2	3		T11	31		T53	2
valid_sources[0x28]	315921	1			T2	4		T3	23		T11	57
valid_sources[0x29]	449827	1			T11	23		T53	4		T55	3
valid_sources[0x2a]	312459	1			T2	3		T11	22		T55	3
valid_sources[0x2b]	317554	1			T2	3		T11	24		T53	1
valid_sources[0x2c]	334344	1			T2	3		T11	33		T53	1
valid_sources[0x2d]	313782	1			T11	68		T53	6		T55	1
valid_sources[0x2e]	315636	1			T2	1		T11	6		T53	2
valid_sources[0x2f]	312710	1			T2	2		T11	12		T53	2
valid_sources[0x30]	699927	1			T2	1		T11	24		T53	2
valid_sources[0x31]	309672	1			T2	4		T3	1		T11	84
valid_sources[0x32]	317444	1			T2	2		T11	30		T53	6
valid_sources[0x33]	316380	1			T2	4		T11	1		T53	2
valid_sources[0x34]	500122	1			T2	5		T11	26		T55	3
valid_sources[0x35]	319686	1			T2	1		T11	60		T53	4
valid_sources[0x36]	387954	1			T2	3		T11	31		T53	3
valid_sources[0x37]	380616	1			T2	2		T11	4		T53	1
valid_sources[0x38]	313195	1			T2	2		T11	29		T53	3
valid_sources[0x39]	315918	1			T2	3		T11	72		T55	2
valid_sources[0x3a]	318734	1			T2	2		T11	36		T53	1
valid_sources[0x3b]	313554	1			T2	3		T11	46		T53	1
valid_sources[0x3c]	426381	1			T2	4		T11	75		T55	3
valid_sources[0x3d]	316351	1			T2	6		T11	39		T51	3
valid_sources[0x3e]	317915	1			T2	1		T11	20		T53	1
valid_sources[0x3f]	522100	1			T2	3		T11	67		T62	2
valid_sources[0x40]	316242	1			T2	3		T11	65		T53	1
valid_sources[0x41]	316361	1			T2	2		T11	31		T53	3
valid_sources[0x42]	488465	1			T2	2		T11	10		T55	3
valid_sources[0x43]	322094	1			T2	2		T11	16		T53	2
valid_sources[0x44]	312493	1			T2	4		T11	9		T55	3
valid_sources[0x45]	314180	1			T2	6		T11	69		T53	1
valid_sources[0x46]	314004	1			T2	4		T11	32		T53	3
valid_sources[0x47]	314926	1			T2	4		T11	34		T53	2
valid_sources[0x48]	316719	1			T2	2		T11	32		T53	2
valid_sources[0x49]	313443	1			T2	5		T3	12		T11	26
valid_sources[0x4a]	315559	1			T2	3		T3	4		T11	32
valid_sources[0x4b]	313353	1			T2	1		T11	117		T53	2
valid_sources[0x4c]	1395422	1			T2	7		T11	23		T53	4
valid_sources[0x4d]	315274	1			T2	2		T3	23		T11	74
valid_sources[0x4e]	316298	1			T2	1		T11	19		T53	2
valid_sources[0x4f]	1245280	1			T2	2		T11	30		T53	1
valid_sources[0x50]	1418422	1			T2	5		T11	36		T53	1
valid_sources[0x51]	322137	1			T11	7		T53	2		T55	4
valid_sources[0x52]	693999	1			T2	6		T11	69		T53	1
valid_sources[0x53]	316124	1			T2	3		T11	58		T53	1
valid_sources[0x54]	368931	1			T2	6		T11	73		T53	3
valid_sources[0x55]	331754	1			T2	8		T11	12		T55	2
valid_sources[0x56]	328841	1			T2	1		T11	51		T49	11725
valid_sources[0x57]	322321	1			T2	1		T3	3		T11	48
valid_sources[0x58]	564607	1			T3	1		T11	64		T53	1
valid_sources[0x59]	319335	1			T2	6		T11	15		T53	1
valid_sources[0x5a]	494414	1			T2	3		T11	11		T53	1
valid_sources[0x5b]	315633	1			T2	4		T11	28		T53	2
valid_sources[0x5c]	315391	1			T11	62		T53	2		T55	2
valid_sources[0x5d]	319464	1			T2	2		T11	42		T53	3
valid_sources[0x5e]	316462	1			T2	1		T3	8		T11	43
valid_sources[0x5f]	459392	1			T2	2		T11	73		T53	3
valid_sources[0x60]	524780	1			T2	2		T11	76		T53	3
valid_sources[0x61]	312472	1			T2	3		T3	12		T11	45
valid_sources[0x62]	318077	1			T2	7		T11	21		T55	1
valid_sources[0x63]	315383	1			T2	1		T11	40		T53	2
valid_sources[0x64]	313965	1			T2	2		T11	32		T55	1
valid_sources[0x65]	314692	1			T2	1		T11	9		T53	3
valid_sources[0x66]	311292	1			T2	4		T11	37		T53	5
valid_sources[0x67]	327941	1			T2	2		T11	59		T53	1
valid_sources[0x68]	313772	1			T2	7		T11	26		T53	4
valid_sources[0x69]	316172	1			T2	2		T11	49		T53	1
valid_sources[0x6a]	318024	1			T2	3		T3	9		T11	84
valid_sources[0x6b]	426101	1			T2	2		T11	51		T53	2
valid_sources[0x6c]	313129	1			T2	4		T11	100		T53	1
valid_sources[0x6d]	314400	1			T2	5		T3	4		T11	26
valid_sources[0x6e]	318209	1			T2	2		T11	33		T53	2
valid_sources[0x6f]	318296	1			T3	2		T11	62		T53	3
valid_sources[0x70]	440070	1			T2	5		T3	1		T11	46
valid_sources[0x71]	338270	1			T2	6		T3	23		T11	66
valid_sources[0x72]	316989	1			T2	3		T11	39		T53	2
valid_sources[0x73]	414442	1			T2	2		T11	21		T53	3
valid_sources[0x74]	412575	1			T2	1		T11	12		T53	1
valid_sources[0x75]	315727	1			T2	5		T11	32		T53	2
valid_sources[0x76]	317475	1			T2	4		T11	33		T51	3
valid_sources[0x77]	326853	1			T2	1		T11	16		T9	88
valid_sources[0x78]	317230	1			T2	3		T11	11		T53	1
valid_sources[0x79]	312346	1			T2	6		T11	26		T53	1
valid_sources[0x7a]	950351	1			T11	82		T9	95		T53	1
valid_sources[0x7b]	339229	1			T2	2		T11	52		T53	3
valid_sources[0x7c]	314116	1			T2	2		T11	61		T53	1
valid_sources[0x7d]	359406	1			T2	4		T11	27		T53	3
valid_sources[0x7e]	317680	1			T2	2		T11	16		T10	14
valid_sources[0x7f]	317680	1			T2	3		T11	28		T53	3
valid_sources[0x80]	312334	1			T2	1		T11	34		T53	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21630640

1

T1

94

T2

159

T3

9

values[0x0]

all_enables

biggest_size

14556433

1

T1

120

T2

137

T3

99

values[0x1]

all_enables

biggest_size

13087106

1

T1

107

T2

146

T3

118