Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

49955403

1

T1

249

T2

328

T3

70

full_word

49278754

1

T1

321

T2

442

T3

226

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	99233877	1			T1	570		T2	770		T3	296
auto[TlIntgErrCmd]	95	1			T135	3		T136	8		T137	1
auto[TlIntgErrData]	83	1			T135	2		T136	7		T137	3
auto[TlIntgErrBoth]	102	1			T135	5		T136	5		T137	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54076862

1

T1

233

T2

391

T3

62

auto[1]

45157295

1

T1

337

T2

379

T3

234

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	32444827	1			T1	139		T2	232		T3	53
auto[TlIntgErrNone]	partial	auto[1]	17510314	1			T1	110		T2	96		T3	17
auto[TlIntgErrNone]	full_word	auto[0]	21631904	1			T1	94		T2	159		T3	9
auto[TlIntgErrNone]	full_word	auto[1]	27646832	1			T1	227		T2	283		T3	217
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T135	2		T136	5		T183	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T135	1		T136	3		T137	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T184	1		T185	1		T186	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T135	1		T136	3		T137	3
auto[TlIntgErrData]	partial	auto[1]	32	1			T136	4		T183	2		T184	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T135	1		T183	1		T187	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T183	1		T186	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T135	1		T136	3		T137	3
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T135	3		T136	2		T137	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T185	1		T188	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T135	1		T183	2		T186	1