Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	650724605	13971	0	0
entropy_period_rd_A	650724605	1554	0	0
intr_enable_rd_A	650724605	2458	0	0
prefix_0_rd_A	650724605	1610	0	0
prefix_10_rd_A	650724605	1699	0	0
prefix_1_rd_A	650724605	1735	0	0
prefix_2_rd_A	650724605	1706	0	0
prefix_3_rd_A	650724605	1668	0	0
prefix_4_rd_A	650724605	1771	0	0
prefix_5_rd_A	650724605	1789	0	0
prefix_6_rd_A	650724605	1704	0	0
prefix_7_rd_A	650724605	1640	0	0
prefix_8_rd_A	650724605	1603	0	0
prefix_9_rd_A	650724605	1682	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650724605	13971	0	0
T35	347183	5052	0	0
T37	375810	0	0	0
T67	169737	2310	0	0
T68	0	3362	0	0
T77	349334	0	0	0
T135	0	1	0	0
T136	0	2	0	0
T141	0	34	0	0
T142	0	2	0	0
T143	0	126	0	0
T144	0	5	0	0
T145	0	133	0	0
T146	351320	0	0	0
T147	995898	0	0	0
T148	463121	0	0	0
T149	116600	0	0	0
T150	51551	0	0	0
T151	1437	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650724605	1554	0	0
T118	8918	28	0	0
T122	12739	96	0	0
T137	11836	76	0	0
T164	2693	5	0	0
T165	5705	5	0	0
T166	26545	144	0	0
T167	2670	11	0	0
T168	5845	15	0	0
T169	63208	48	0	0
T170	22627	109	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650724605	2458	0	0
T118	8918	71	0	0
T137	11836	85	0	0
T138	1443	10	0	0
T144	3693	2	0	0
T164	2693	13	0	0
T165	5705	45	0	0
T166	26545	224	0	0
T167	2670	2	0	0
T168	5845	8	0	0
T171	1053	12	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650724605	1610	0	0
T118	8918	15	0	0
T137	11836	37	0	0
T144	3693	8	0	0
T164	2693	6	0	0
T165	5705	16	0	0
T166	26545	168	0	0
T167	2670	8	0	0
T168	5845	7	0	0
T169	63208	146	0	0
T170	22627	131	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650724605	1699	0	0
T118	8918	12	0	0
T137	11836	49	0	0
T144	3693	10	0	0
T164	2693	4	0	0
T165	5705	4	0	0
T166	26545	227	0	0
T167	2670	12	0	0
T168	5845	6	0	0
T169	63208	153	0	0
T170	22627	102	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650724605	1735	0	0
T118	8918	19	0	0
T137	11836	48	0	0
T144	3693	3	0	0
T164	2693	5	0	0
T165	5705	28	0	0
T166	26545	186	0	0
T167	2670	11	0	0
T168	5845	18	0	0
T169	63208	156	0	0
T170	22627	135	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650724605	1706	0	0
T118	8918	33	0	0
T137	11836	38	0	0
T144	3693	2	0	0
T164	2693	9	0	0
T165	5705	27	0	0
T166	26545	198	0	0
T167	2670	2	0	0
T168	5845	6	0	0
T169	63208	145	0	0
T170	22627	111	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650724605	1668	0	0
T118	8918	28	0	0
T137	11836	56	0	0
T144	3693	8	0	0
T164	2693	10	0	0
T165	5705	4	0	0
T166	26545	187	0	0
T167	2670	8	0	0
T168	5845	31	0	0
T169	63208	131	0	0
T170	22627	103	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650724605	1771	0	0
T118	8918	28	0	0
T137	11836	57	0	0
T144	3693	4	0	0
T164	2693	6	0	0
T165	5705	1	0	0
T166	26545	206	0	0
T167	2670	5	0	0
T168	5845	17	0	0
T169	63208	123	0	0
T170	22627	127	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650724605	1789	0	0
T118	8918	33	0	0
T137	11836	41	0	0
T144	3693	8	0	0
T164	2693	8	0	0
T165	5705	31	0	0
T166	26545	208	0	0
T167	2670	1	0	0
T168	5845	12	0	0
T169	63208	166	0	0
T170	22627	73	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650724605	1704	0	0
T118	8918	24	0	0
T137	11836	25	0	0
T144	3693	7	0	0
T164	2693	6	0	0
T165	5705	18	0	0
T166	26545	242	0	0
T167	2670	9	0	0
T168	5845	20	0	0
T169	63208	153	0	0
T170	22627	77	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650724605	1640	0	0
T118	8918	29	0	0
T122	12739	59	0	0
T137	11836	53	0	0
T164	2693	2	0	0
T165	5705	6	0	0
T166	26545	192	0	0
T167	2670	4	0	0
T168	5845	42	0	0
T169	63208	114	0	0
T170	22627	110	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650724605	1603	0	0
T118	8918	29	0	0
T137	11836	37	0	0
T144	3693	3	0	0
T164	2693	9	0	0
T165	5705	20	0	0
T166	26545	209	0	0
T167	2670	16	0	0
T168	5845	39	0	0
T169	63208	137	0	0
T170	22627	100	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650724605	1682	0	0
T118	8918	45	0	0
T137	11836	34	0	0
T144	3693	6	0	0
T164	2693	9	0	0
T165	5705	29	0	0
T166	26545	217	0	0
T167	2670	9	0	0
T168	5845	23	0	0
T169	63208	121	0	0
T170	22627	90	0	0