Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
162990 |
1 |
|
|
T4 |
1811 |
|
T5 |
202 |
|
T6 |
2061 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
79659 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
64380 |
1 |
|
|
T4 |
1783 |
|
T5 |
198 |
|
T6 |
2031 |
seven_bytes |
2738 |
1 |
|
|
T11 |
32 |
|
T29 |
1 |
|
T52 |
8 |
six_bytes |
2756 |
1 |
|
|
T11 |
21 |
|
T29 |
2 |
|
T52 |
12 |
five_bytes |
2675 |
1 |
|
|
T11 |
29 |
|
T52 |
9 |
|
T13 |
8 |
four_bytes |
2735 |
1 |
|
|
T11 |
30 |
|
T52 |
10 |
|
T13 |
17 |
three_bytes |
2667 |
1 |
|
|
T11 |
21 |
|
T52 |
10 |
|
T13 |
6 |
two_bytes |
2747 |
1 |
|
|
T11 |
20 |
|
T52 |
8 |
|
T13 |
12 |
one_byte |
2633 |
1 |
|
|
T11 |
17 |
|
T52 |
11 |
|
T13 |
7 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
159754 |
1 |
|
|
T4 |
1755 |
|
T5 |
194 |
|
T6 |
2001 |
auto[1] |
3236 |
1 |
|
|
T4 |
56 |
|
T5 |
8 |
|
T6 |
60 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
162990 |
1 |
|
|
T4 |
1811 |
|
T5 |
202 |
|
T6 |
2061 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
162978 |
1 |
|
|
T4 |
1811 |
|
T5 |
202 |
|
T6 |
2061 |
auto[1] |
12 |
1 |
|
|
T102 |
1 |
|
T180 |
1 |
|
T98 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1164 |
1 |
|
|
T4 |
28 |
|
T5 |
4 |
|
T6 |
30 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3236 |
1 |
|
|
T4 |
56 |
|
T5 |
8 |
|
T6 |
60 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164845 |
1 |
|
|
T9 |
29 |
|
T4 |
3548 |
|
T5 |
275 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
78639 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
67685 |
1 |
|
|
T9 |
29 |
|
T4 |
3494 |
|
T5 |
270 |
seven_bytes |
2626 |
1 |
|
|
T11 |
9 |
|
T12 |
7 |
|
T13 |
19 |
six_bytes |
2600 |
1 |
|
|
T11 |
7 |
|
T52 |
2 |
|
T12 |
9 |
five_bytes |
2662 |
1 |
|
|
T11 |
15 |
|
T52 |
3 |
|
T12 |
3 |
four_bytes |
2648 |
1 |
|
|
T11 |
14 |
|
T52 |
4 |
|
T12 |
3 |
three_bytes |
2684 |
1 |
|
|
T11 |
9 |
|
T52 |
2 |
|
T12 |
3 |
two_bytes |
2604 |
1 |
|
|
T11 |
19 |
|
T52 |
5 |
|
T12 |
3 |
one_byte |
2697 |
1 |
|
|
T11 |
15 |
|
T52 |
3 |
|
T12 |
5 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
161415 |
1 |
|
|
T9 |
29 |
|
T4 |
3440 |
|
T5 |
265 |
auto[1] |
3430 |
1 |
|
|
T4 |
108 |
|
T5 |
10 |
|
T6 |
74 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164845 |
1 |
|
|
T9 |
29 |
|
T4 |
3548 |
|
T5 |
275 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164827 |
1 |
|
|
T9 |
29 |
|
T4 |
3547 |
|
T5 |
275 |
auto[1] |
18 |
1 |
|
|
T4 |
1 |
|
T6 |
3 |
|
T97 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1271 |
1 |
|
|
T4 |
54 |
|
T5 |
5 |
|
T6 |
37 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3430 |
1 |
|
|
T4 |
108 |
|
T5 |
10 |
|
T6 |
74 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350297 |
1 |
|
|
T1 |
9 |
|
T8 |
46 |
|
T4 |
3712 |
auto[1] |
657 |
1 |
|
|
T8 |
4 |
|
T4 |
60 |
|
T5 |
13 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
173564 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
136208 |
1 |
|
|
T1 |
6 |
|
T8 |
36 |
|
T4 |
3712 |
seven_bytes |
5886 |
1 |
|
|
T11 |
25 |
|
T29 |
1 |
|
T52 |
4 |
six_bytes |
5906 |
1 |
|
|
T11 |
21 |
|
T52 |
8 |
|
T12 |
6 |
five_bytes |
5812 |
1 |
|
|
T11 |
27 |
|
T52 |
6 |
|
T12 |
13 |
four_bytes |
5964 |
1 |
|
|
T11 |
34 |
|
T52 |
8 |
|
T12 |
11 |
three_bytes |
5756 |
1 |
|
|
T11 |
18 |
|
T52 |
10 |
|
T12 |
14 |
two_bytes |
6005 |
1 |
|
|
T11 |
26 |
|
T52 |
8 |
|
T12 |
15 |
one_byte |
5853 |
1 |
|
|
T11 |
18 |
|
T52 |
4 |
|
T12 |
17 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
343294 |
1 |
|
|
T1 |
3 |
|
T8 |
22 |
|
T4 |
3652 |
auto[1] |
7660 |
1 |
|
|
T1 |
6 |
|
T8 |
28 |
|
T4 |
120 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350954 |
1 |
|
|
T1 |
9 |
|
T8 |
50 |
|
T4 |
3772 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350822 |
1 |
|
|
T1 |
7 |
|
T8 |
46 |
|
T4 |
3772 |
auto[1] |
132 |
1 |
|
|
T1 |
2 |
|
T8 |
4 |
|
T10 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2886 |
1 |
|
|
T1 |
3 |
|
T8 |
14 |
|
T4 |
60 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
7660 |
1 |
|
|
T1 |
6 |
|
T8 |
28 |
|
T4 |
120 |