Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47097858	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

47621087

1

T1

463

T2

436

T3

310

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51953304	1			T1	357		T2	401		T3	221
values[0x0]	20719532	1			T1	81		T2	199		T3	148
values[0x1]	22046109	1			T1	68		T2	214		T3	142

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36234454	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

58484491

1

T1

476

T2

528

T3

357

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	289929	1			T1	2		T14	51		T46	31
valid_sources[0x01]	305758	1			T1	5		T9	1		T14	194
valid_sources[0x02]	287366	1			T1	2		T2	2		T3	2
valid_sources[0x03]	286646	1			T1	4		T3	37		T47	1
valid_sources[0x04]	288714	1			T1	2		T14	5		T46	57
valid_sources[0x05]	284847	1			T1	2		T2	19		T7	3
valid_sources[0x06]	285483	1			T1	3		T7	7		T9	1
valid_sources[0x07]	446534	1			T1	2		T2	22		T7	1
valid_sources[0x08]	288585	1			T1	3		T7	1		T46	53
valid_sources[0x09]	285265	1			T7	1		T9	1		T14	3
valid_sources[0x0a]	289191	1			T1	2		T2	21		T7	7
valid_sources[0x0b]	1103900	1			T1	1		T2	27		T9	1
valid_sources[0x0c]	499849	1			T1	1		T14	44		T46	65
valid_sources[0x0d]	321513	1			T9	1		T14	13		T46	30
valid_sources[0x0e]	291288	1			T1	3		T7	1		T9	1
valid_sources[0x0f]	283700	1			T1	1		T2	46		T14	2
valid_sources[0x10]	286419	1			T1	2		T3	1		T7	1
valid_sources[0x11]	290937	1			T1	2		T3	25		T7	7
valid_sources[0x12]	286618	1			T1	2		T7	1		T9	1
valid_sources[0x13]	284501	1			T7	3		T9	1		T46	51
valid_sources[0x14]	290180	1			T1	1		T14	3		T46	39
valid_sources[0x15]	707614	1			T1	5		T7	9		T9	1
valid_sources[0x16]	560674	1			T1	5		T7	4		T9	1
valid_sources[0x17]	289255	1			T1	3		T7	1		T14	88
valid_sources[0x18]	946256	1			T1	1		T7	3		T14	76
valid_sources[0x19]	290950	1			T1	5		T2	9		T9	1
valid_sources[0x1a]	289823	1			T1	1		T7	4		T46	19
valid_sources[0x1b]	484324	1			T1	4		T2	14		T46	43
valid_sources[0x1c]	289103	1			T1	2		T7	2		T14	4
valid_sources[0x1d]	284208	1			T2	88		T7	1		T46	43
valid_sources[0x1e]	284958	1			T1	3		T7	2		T14	4
valid_sources[0x1f]	295241	1			T1	4		T2	12		T7	2
valid_sources[0x20]	310961	1			T14	29		T46	57		T31	2
valid_sources[0x21]	438452	1			T1	2		T47	1		T9	1
valid_sources[0x22]	285899	1			T7	5		T46	44		T31	12
valid_sources[0x23]	288787	1			T1	3		T14	152		T46	19
valid_sources[0x24]	283019	1			T7	2		T9	1		T46	46
valid_sources[0x25]	1074060	1			T1	2		T14	227		T46	29
valid_sources[0x26]	288630	1			T1	1		T7	7		T46	61
valid_sources[0x27]	285286	1			T1	4		T7	1		T9	1
valid_sources[0x28]	398492	1			T1	3		T7	1		T46	72
valid_sources[0x29]	287130	1			T1	2		T2	12		T7	1
valid_sources[0x2a]	288477	1			T1	1		T47	1		T9	1
valid_sources[0x2b]	287663	1			T1	2		T7	6		T14	2
valid_sources[0x2c]	327097	1			T1	10		T14	2		T46	23
valid_sources[0x2d]	304516	1			T7	7		T14	1		T46	64
valid_sources[0x2e]	293345	1			T1	1		T7	1		T9	1
valid_sources[0x2f]	472775	1			T47	1		T7	2		T14	2
valid_sources[0x30]	399905	1			T1	6		T3	23		T47	1
valid_sources[0x31]	456290	1			T1	2		T7	1		T9	1
valid_sources[0x32]	295203	1			T1	2		T14	1		T46	62
valid_sources[0x33]	391686	1			T1	6		T3	22		T14	2
valid_sources[0x34]	392951	1			T1	1		T2	26		T7	1
valid_sources[0x35]	406588	1			T1	3		T7	2		T9	2
valid_sources[0x36]	285922	1			T9	1		T14	30		T46	22
valid_sources[0x37]	285561	1			T1	1		T9	1		T14	2
valid_sources[0x38]	287592	1			T1	1		T7	2		T46	72
valid_sources[0x39]	286470	1			T1	2		T47	1		T7	2
valid_sources[0x3a]	287343	1			T1	1		T3	26		T7	1
valid_sources[0x3b]	323306	1			T1	2		T47	2		T9	1
valid_sources[0x3c]	286295	1			T1	1		T14	2		T46	9
valid_sources[0x3d]	388089	1			T1	2		T46	21		T31	26
valid_sources[0x3e]	286042	1			T1	5		T9	1		T14	10
valid_sources[0x3f]	409029	1			T1	1		T7	1		T46	50
valid_sources[0x40]	287681	1			T1	1		T14	2		T46	89
valid_sources[0x41]	291865	1			T1	1		T47	2		T7	1
valid_sources[0x42]	286071	1			T1	3		T2	17		T7	5
valid_sources[0x43]	285674	1			T1	2		T9	1		T14	18
valid_sources[0x44]	286820	1			T1	4		T9	2		T14	1
valid_sources[0x45]	286447	1			T1	1		T9	1		T46	28
valid_sources[0x46]	429226	1			T1	2		T7	4		T9	1
valid_sources[0x47]	284349	1			T1	1		T7	3		T9	2
valid_sources[0x48]	286101	1			T1	5		T47	3		T7	1
valid_sources[0x49]	286037	1			T1	3		T14	2		T46	59
valid_sources[0x4a]	287694	1			T1	1		T9	1		T46	28
valid_sources[0x4b]	285296	1			T1	2		T9	2		T14	13
valid_sources[0x4c]	287380	1			T1	2		T7	4		T9	1
valid_sources[0x4d]	1199250	1			T14	11		T46	30		T31	9
valid_sources[0x4e]	284274	1			T1	3		T2	16		T3	13
valid_sources[0x4f]	288374	1			T1	3		T3	21		T7	2
valid_sources[0x50]	287915	1			T1	1		T14	60		T46	64
valid_sources[0x51]	286401	1			T1	1		T14	2		T46	34
valid_sources[0x52]	291422	1			T1	2		T14	14		T46	50
valid_sources[0x53]	604070	1			T1	1		T47	2		T7	1
valid_sources[0x54]	407333	1			T1	3		T9	1		T14	1
valid_sources[0x55]	285548	1			T1	1		T7	9		T9	1
valid_sources[0x56]	287600	1			T7	1		T9	1		T46	35
valid_sources[0x57]	285835	1			T1	4		T2	13		T7	2
valid_sources[0x58]	307672	1			T1	2		T2	4		T47	1
valid_sources[0x59]	289571	1			T7	3		T9	2		T14	112
valid_sources[0x5a]	317117	1			T7	3		T9	1		T14	20
valid_sources[0x5b]	285821	1			T1	2		T47	1		T7	3
valid_sources[0x5c]	287082	1			T1	1		T9	1		T14	2
valid_sources[0x5d]	288832	1			T7	1		T9	2		T14	61
valid_sources[0x5e]	287146	1			T1	2		T9	2		T14	4
valid_sources[0x5f]	1178662	1			T1	1		T7	1		T14	180
valid_sources[0x60]	289747	1			T1	3		T47	1		T14	24
valid_sources[0x61]	341142	1			T1	1		T2	8		T9	1
valid_sources[0x62]	362352	1			T1	3		T7	2		T14	2
valid_sources[0x63]	287816	1			T3	1		T14	97		T46	36
valid_sources[0x64]	345402	1			T1	1		T14	1		T46	29
valid_sources[0x65]	284860	1			T1	1		T14	2		T46	35
valid_sources[0x66]	421770	1			T1	1		T46	29		T31	37
valid_sources[0x67]	304560	1			T1	1		T7	4		T14	38
valid_sources[0x68]	282712	1			T1	4		T9	2		T14	3
valid_sources[0x69]	285664	1			T1	2		T7	1		T9	2
valid_sources[0x6a]	290326	1			T1	3		T7	2		T14	57
valid_sources[0x6b]	283468	1			T1	4		T3	8		T9	1
valid_sources[0x6c]	408269	1			T1	2		T14	3		T46	19
valid_sources[0x6d]	293305	1			T1	3		T2	6		T9	1
valid_sources[0x6e]	289441	1			T1	2		T7	5		T14	2
valid_sources[0x6f]	401095	1			T1	1		T14	63		T46	43
valid_sources[0x70]	293768	1			T1	3		T7	4		T9	1
valid_sources[0x71]	289634	1			T1	4		T7	1		T9	1
valid_sources[0x72]	285090	1			T1	1		T14	1		T46	28
valid_sources[0x73]	285790	1			T1	1		T7	2		T14	1
valid_sources[0x74]	285589	1			T2	2		T14	107		T46	70
valid_sources[0x75]	287537	1			T1	1		T46	58		T31	25
valid_sources[0x76]	287433	1			T1	3		T2	13		T7	2
valid_sources[0x77]	286661	1			T1	1		T2	58		T7	5
valid_sources[0x78]	284397	1			T1	1		T7	2		T14	5
valid_sources[0x79]	288961	1			T1	3		T9	1		T14	1
valid_sources[0x7a]	373443	1			T1	1		T9	1		T48	1
valid_sources[0x7b]	395080	1			T9	1		T14	108		T46	55
valid_sources[0x7c]	289358	1			T1	1		T9	1		T46	52
valid_sources[0x7d]	286046	1			T1	3		T2	11		T7	1
valid_sources[0x7e]	290098	1			T1	1		T3	9		T7	1
valid_sources[0x7f]	370516	1			T2	4		T14	60		T46	54
valid_sources[0x80]	310905	1			T1	4		T7	2		T9	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21013359

1

T1

327

T2

155

T3

86

values[0x0]

all_enables

biggest_size

13979932

1

T1

75

T2

143

T3

113

values[0x1]

all_enables

biggest_size

12627796

1

T1

61

T2

138

T3

111