Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

47198266

1

T1

43

T2

378

T3

201

full_word

47627370

1

T1

463

T2

436

T3

310

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	94825356	1			T1	506		T2	814		T3	511
auto[TlIntgErrCmd]	87	1			T137	1		T138	5		T139	4
auto[TlIntgErrData]	96	1			T137	6		T138	6		T139	2
auto[TlIntgErrBoth]	97	1			T137	3		T138	9		T139	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51976074

1

T1

357

T2

401

T3

221

auto[1]

42849562

1

T1

149

T2

413

T3

290

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	30960825	1			T1	30		T2	246		T3	135
auto[TlIntgErrNone]	partial	auto[1]	16237190	1			T1	13		T2	132		T3	66
auto[TlIntgErrNone]	full_word	auto[0]	21015138	1			T1	327		T2	155		T3	86
auto[TlIntgErrNone]	full_word	auto[1]	26612203	1			T1	136		T2	281		T3	224
auto[TlIntgErrCmd]	partial	auto[0]	27	1			T138	3		T139	1		T181	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T138	2		T139	3		T181	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T137	1		T182	2		T183	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T184	1		T185	1		T183	1
auto[TlIntgErrData]	partial	auto[0]	33	1			T137	1		T138	2		T181	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T137	5		T138	4		T139	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T186	2		T187	2		T188	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T189	1		T190	1		T184	2
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T137	1		T138	3		T139	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T137	2		T138	6		T139	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T182	2		T191	1		T192	1