Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	627945439	57742360	0	0
DataKnown_AKnownEnable	627945439	627733872	0	0
DepthKnown_A	627945439	627733872	0	0
RvalidKnown_A	627945439	627733872	0	0
WreadyKnown_A	627945439	627733872	0	0
gen_passthru_fifo.paramCheckPass	934	934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	57742360	0	0
T1	7186	184	0	0
T2	7045	597	0	0
T3	5018	405	0	0
T7	61964	378	0	0
T9	2500	83	0	0
T14	51947	2489	0	0
T31	66509	2438	0	0
T46	108527	7153	0	0
T47	989	28	0	0
T48	823	5	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	627733872	0	0
T1	7186	7090	0	0
T2	7045	6982	0	0
T3	5018	4948	0	0
T7	61964	61880	0	0
T9	2500	2324	0	0
T14	51947	51892	0	0
T31	66509	66415	0	0
T46	108527	108456	0	0
T47	989	911	0	0
T48	823	762	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	627733872	0	0
T1	7186	7090	0	0
T2	7045	6982	0	0
T3	5018	4948	0	0
T7	61964	61880	0	0
T9	2500	2324	0	0
T14	51947	51892	0	0
T31	66509	66415	0	0
T46	108527	108456	0	0
T47	989	911	0	0
T48	823	762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	627733872	0	0
T1	7186	7090	0	0
T2	7045	6982	0	0
T3	5018	4948	0	0
T7	61964	61880	0	0
T9	2500	2324	0	0
T14	51947	51892	0	0
T31	66509	66415	0	0
T46	108527	108456	0	0
T47	989	911	0	0
T48	823	762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	627733872	0	0
T1	7186	7090	0	0
T2	7045	6982	0	0
T3	5018	4948	0	0
T7	61964	61880	0	0
T9	2500	2324	0	0
T14	51947	51892	0	0
T31	66509	66415	0	0
T46	108527	108456	0	0
T47	989	911	0	0
T48	823	762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	934	934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T31	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	627945439	110934506	0	0
DataKnown_AKnownEnable	627945439	627733872	0	0
DepthKnown_A	627945439	627733872	0	0
RvalidKnown_A	627945439	627733872	0	0
WreadyKnown_A	627945439	627733872	0	0
gen_passthru_fifo.paramCheckPass	934	934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	110934506	0	0
T1	7186	796	0	0
T2	7045	597	0	0
T3	5018	405	0	0
T7	61964	1668	0	0
T9	2500	83	0	0
T14	51947	11313	0	0
T31	66509	11020	0	0
T46	108527	7153	0	0
T47	989	111	0	0
T48	823	5	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	627733872	0	0
T1	7186	7090	0	0
T2	7045	6982	0	0
T3	5018	4948	0	0
T7	61964	61880	0	0
T9	2500	2324	0	0
T14	51947	51892	0	0
T31	66509	66415	0	0
T46	108527	108456	0	0
T47	989	911	0	0
T48	823	762	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	627733872	0	0
T1	7186	7090	0	0
T2	7045	6982	0	0
T3	5018	4948	0	0
T7	61964	61880	0	0
T9	2500	2324	0	0
T14	51947	51892	0	0
T31	66509	66415	0	0
T46	108527	108456	0	0
T47	989	911	0	0
T48	823	762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	627733872	0	0
T1	7186	7090	0	0
T2	7045	6982	0	0
T3	5018	4948	0	0
T7	61964	61880	0	0
T9	2500	2324	0	0
T14	51947	51892	0	0
T31	66509	66415	0	0
T46	108527	108456	0	0
T47	989	911	0	0
T48	823	762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	627733872	0	0
T1	7186	7090	0	0
T2	7045	6982	0	0
T3	5018	4948	0	0
T7	61964	61880	0	0
T9	2500	2324	0	0
T14	51947	51892	0	0
T31	66509	66415	0	0
T46	108527	108456	0	0
T47	989	911	0	0
T48	823	762	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	934	934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T31	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0