Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	627945439	18719	0	0
entropy_period_rd_A	627945439	2246	0	0
intr_enable_rd_A	627945439	3044	0	0
prefix_0_rd_A	627945439	2246	0	0
prefix_10_rd_A	627945439	2358	0	0
prefix_1_rd_A	627945439	2208	0	0
prefix_2_rd_A	627945439	2269	0	0
prefix_3_rd_A	627945439	2353	0	0
prefix_4_rd_A	627945439	2281	0	0
prefix_5_rd_A	627945439	2412	0	0
prefix_6_rd_A	627945439	2095	0	0
prefix_7_rd_A	627945439	2304	0	0
prefix_8_rd_A	627945439	2224	0	0
prefix_9_rd_A	627945439	2273	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	18719	0	0
T12	34288	0	0	0
T13	582970	0	0	0
T29	227792	1324	0	0
T34	0	1842	0	0
T52	51750	0	0	0
T54	4219	0	0	0
T83	0	4494	0	0
T93	0	702	0	0
T94	0	2168	0	0
T132	29086	0	0	0
T135	7609	0	0	0
T136	204169	0	0	0
T137	0	1	0	0
T138	0	2	0	0
T143	0	4590	0	0
T144	0	174	0	0
T145	0	4	0	0
T147	255415	0	0	0
T148	548816	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	2246	0	0
T12	34288	0	0	0
T13	582970	0	0	0
T29	227792	14	0	0
T34	0	17	0	0
T52	51750	0	0	0
T54	4219	0	0	0
T94	0	36	0	0
T111	0	50	0	0
T132	29086	0	0	0
T135	7609	0	0	0
T136	204169	0	0	0
T147	255415	0	0	0
T148	548816	0	0	0
T163	0	11	0	0
T164	0	10	0	0
T165	0	90	0	0
T166	0	445	0	0
T167	0	10	0	0
T168	0	368	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	3044	0	0
T12	34288	0	0	0
T13	582970	0	0	0
T29	227792	19	0	0
T34	0	21	0	0
T52	51750	0	0	0
T54	4219	0	0	0
T94	0	31	0	0
T111	0	82	0	0
T132	29086	0	0	0
T135	7609	0	0	0
T136	204169	0	0	0
T140	0	7	0	0
T147	255415	0	0	0
T148	548816	0	0	0
T163	0	8	0	0
T164	0	7	0	0
T165	0	117	0	0
T166	0	499	0	0
T169	0	29	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	2246	0	0
T12	34288	0	0	0
T13	582970	0	0	0
T29	227792	19	0	0
T34	0	23	0	0
T52	51750	0	0	0
T54	4219	0	0	0
T94	0	43	0	0
T111	0	50	0	0
T132	29086	0	0	0
T135	7609	0	0	0
T136	204169	0	0	0
T147	255415	0	0	0
T148	548816	0	0	0
T163	0	7	0	0
T164	0	14	0	0
T165	0	163	0	0
T166	0	444	0	0
T167	0	1	0	0
T170	0	29	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	2358	0	0
T12	34288	0	0	0
T13	582970	0	0	0
T29	227792	27	0	0
T34	0	44	0	0
T52	51750	0	0	0
T54	4219	0	0	0
T94	0	75	0	0
T111	0	50	0	0
T132	29086	0	0	0
T135	7609	0	0	0
T136	204169	0	0	0
T147	255415	0	0	0
T148	548816	0	0	0
T163	0	15	0	0
T164	0	21	0	0
T165	0	128	0	0
T166	0	464	0	0
T167	0	7	0	0
T170	0	5	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	2208	0	0
T12	34288	0	0	0
T13	582970	0	0	0
T29	227792	39	0	0
T34	0	19	0	0
T52	51750	0	0	0
T54	4219	0	0	0
T94	0	42	0	0
T111	0	50	0	0
T132	29086	0	0	0
T135	7609	0	0	0
T136	204169	0	0	0
T147	255415	0	0	0
T148	548816	0	0	0
T163	0	17	0	0
T164	0	3	0	0
T165	0	133	0	0
T166	0	408	0	0
T168	0	404	0	0
T170	0	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	2269	0	0
T12	34288	0	0	0
T13	582970	0	0	0
T29	227792	29	0	0
T34	0	9	0	0
T52	51750	0	0	0
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T94	0	43	0	0
T111	0	35	0	0
T132	29086	0	0	0
T135	7609	0	0	0
T136	204169	0	0	0
T147	255415	0	0	0
T148	548816	0	0	0
T163	0	6	0	0
T164	0	21	0	0
T165	0	128	0	0
T166	0	448	0	0
T168	0	432	0	0
T170	0	37	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	2353	0	0
T12	34288	0	0	0
T13	582970	0	0	0
T29	227792	18	0	0
T34	0	10	0	0
T52	51750	0	0	0
T54	4219	0	0	0
T94	0	23	0	0
T111	0	39	0	0
T132	29086	0	0	0
T135	7609	0	0	0
T136	204169	0	0	0
T147	255415	0	0	0
T148	548816	0	0	0
T163	0	12	0	0
T164	0	38	0	0
T165	0	148	0	0
T166	0	407	0	0
T167	0	4	0	0
T170	0	21	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	2281	0	0
T12	34288	0	0	0
T13	582970	0	0	0
T29	227792	25	0	0
T34	0	20	0	0
T52	51750	0	0	0
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T94	0	42	0	0
T111	0	59	0	0
T132	29086	0	0	0
T135	7609	0	0	0
T136	204169	0	0	0
T147	255415	0	0	0
T148	548816	0	0	0
T163	0	5	0	0
T164	0	37	0	0
T165	0	175	0	0
T166	0	420	0	0
T168	0	386	0	0
T170	0	22	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	2412	0	0
T12	34288	0	0	0
T13	582970	0	0	0
T29	227792	23	0	0
T34	0	26	0	0
T52	51750	0	0	0
T54	4219	0	0	0
T94	0	44	0	0
T111	0	55	0	0
T132	29086	0	0	0
T135	7609	0	0	0
T136	204169	0	0	0
T147	255415	0	0	0
T148	548816	0	0	0
T163	0	12	0	0
T164	0	35	0	0
T165	0	144	0	0
T166	0	439	0	0
T168	0	418	0	0
T170	0	26	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	2095	0	0
T12	34288	0	0	0
T13	582970	0	0	0
T29	227792	18	0	0
T34	0	17	0	0
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T166	0	447	0	0
T167	0	4	0	0
T170	0	12	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	2304	0	0
T12	34288	0	0	0
T13	582970	0	0	0
T29	227792	21	0	0
T34	0	14	0	0
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T94	0	76	0	0
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T135	7609	0	0	0
T136	204169	0	0	0
T147	255415	0	0	0
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T163	0	9	0	0
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T165	0	124	0	0
T166	0	458	0	0
T168	0	484	0	0
T170	0	20	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	2224	0	0
T12	34288	0	0	0
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T166	0	419	0	0
T168	0	436	0	0
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prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	627945439	2273	0	0
T12	34288	0	0	0
T13	582970	0	0	0
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