Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	601868762	10849	0	0
entropy_period_rd_A	601868762	1760	0	0
intr_enable_rd_A	601868762	2510	0	0
prefix_0_rd_A	601868762	1579	0	0
prefix_10_rd_A	601868762	1654	0	0
prefix_1_rd_A	601868762	1519	0	0
prefix_2_rd_A	601868762	1629	0	0
prefix_3_rd_A	601868762	1750	0	0
prefix_4_rd_A	601868762	1484	0	0
prefix_5_rd_A	601868762	1654	0	0
prefix_6_rd_A	601868762	1612	0	0
prefix_7_rd_A	601868762	1563	0	0
prefix_8_rd_A	601868762	1592	0	0
prefix_9_rd_A	601868762	1528	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	10849	0	0
T5	197082	0	0	0
T10	261666	0	0	0
T12	173067	998	0	0
T17	2126	0	0	0
T22	4131	0	0	0
T34	136608	0	0	0
T41	0	3582	0	0
T75	119373	0	0	0
T79	0	231	0	0
T90	2444	0	0	0
T94	0	1057	0	0
T104	1738	0	0	0
T105	4239	0	0	0
T128	0	2	0	0
T129	0	4	0	0
T131	0	2189	0	0
T135	0	191	0	0
T136	0	4	0	0
T137	0	78	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	1760	0	0
T5	197082	0	0	0
T10	261666	0	0	0
T12	173067	18	0	0
T17	2126	0	0	0
T22	4131	0	0	0
T34	136608	0	0	0
T41	0	36	0	0
T75	119373	0	0	0
T90	2444	0	0	0
T104	1738	0	0	0
T105	4239	0	0	0
T106	0	1	0	0
T107	0	36	0	0
T118	0	3	0	0
T128	0	118	0	0
T133	0	7	0	0
T136	0	16	0	0
T150	0	2	0	0
T151	0	212	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	2510	0	0
T5	197082	0	0	0
T10	261666	0	0	0
T12	173067	13	0	0
T17	2126	0	0	0
T22	4131	0	0	0
T34	136608	0	0	0
T41	0	31	0	0
T75	119373	0	0	0
T90	2444	0	0	0
T104	1738	0	0	0
T105	4239	0	0	0
T106	0	7	0	0
T107	0	35	0	0
T128	0	150	0	0
T133	0	12	0	0
T134	0	11	0	0
T136	0	10	0	0
T150	0	44	0	0
T151	0	231	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	1579	0	0
T5	197082	0	0	0
T10	261666	0	0	0
T12	173067	15	0	0
T17	2126	0	0	0
T22	4131	0	0	0
T34	136608	0	0	0
T41	0	43	0	0
T75	119373	0	0	0
T90	2444	0	0	0
T104	1738	0	0	0
T105	4239	0	0	0
T106	0	10	0	0
T107	0	22	0	0
T128	0	79	0	0
T129	0	88	0	0
T133	0	5	0	0
T136	0	9	0	0
T150	0	42	0	0
T151	0	266	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	1654	0	0
T5	197082	0	0	0
T10	261666	0	0	0
T12	173067	26	0	0
T17	2126	0	0	0
T22	4131	0	0	0
T34	136608	0	0	0
T41	0	4	0	0
T75	119373	0	0	0
T90	2444	0	0	0
T104	1738	0	0	0
T105	4239	0	0	0
T106	0	7	0	0
T107	0	23	0	0
T118	0	5	0	0
T128	0	92	0	0
T133	0	1	0	0
T136	0	9	0	0
T150	0	52	0	0
T151	0	184	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	1519	0	0
T5	197082	0	0	0
T10	261666	0	0	0
T12	173067	21	0	0
T17	2126	0	0	0
T22	4131	0	0	0
T34	136608	0	0	0
T41	0	14	0	0
T75	119373	0	0	0
T90	2444	0	0	0
T104	1738	0	0	0
T105	4239	0	0	0
T106	0	10	0	0
T107	0	26	0	0
T118	0	2	0	0
T128	0	78	0	0
T133	0	7	0	0
T136	0	7	0	0
T150	0	29	0	0
T151	0	193	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	1629	0	0
T5	197082	0	0	0
T10	261666	0	0	0
T12	173067	27	0	0
T17	2126	0	0	0
T22	4131	0	0	0
T34	136608	0	0	0
T41	0	24	0	0
T75	119373	0	0	0
T90	2444	0	0	0
T104	1738	0	0	0
T105	4239	0	0	0
T106	0	5	0	0
T107	0	30	0	0
T128	0	40	0	0
T129	0	75	0	0
T133	0	8	0	0
T136	0	16	0	0
T150	0	1	0	0
T151	0	197	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	1750	0	0
T5	197082	0	0	0
T10	261666	0	0	0
T12	173067	20	0	0
T17	2126	0	0	0
T22	4131	0	0	0
T34	136608	0	0	0
T41	0	25	0	0
T75	119373	0	0	0
T90	2444	0	0	0
T104	1738	0	0	0
T105	4239	0	0	0
T106	0	9	0	0
T107	0	15	0	0
T128	0	95	0	0
T129	0	95	0	0
T133	0	14	0	0
T136	0	13	0	0
T150	0	33	0	0
T151	0	251	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	1484	0	0
T5	197082	0	0	0
T10	261666	0	0	0
T12	173067	20	0	0
T17	2126	0	0	0
T22	4131	0	0	0
T34	136608	0	0	0
T41	0	24	0	0
T75	119373	0	0	0
T90	2444	0	0	0
T104	1738	0	0	0
T105	4239	0	0	0
T106	0	13	0	0
T107	0	27	0	0
T128	0	61	0	0
T129	0	76	0	0
T133	0	12	0	0
T136	0	5	0	0
T150	0	43	0	0
T151	0	194	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	1654	0	0
T5	197082	0	0	0
T10	261666	0	0	0
T12	173067	14	0	0
T17	2126	0	0	0
T22	4131	0	0	0
T34	136608	0	0	0
T41	0	20	0	0
T75	119373	0	0	0
T90	2444	0	0	0
T104	1738	0	0	0
T105	4239	0	0	0
T106	0	13	0	0
T107	0	23	0	0
T128	0	74	0	0
T129	0	66	0	0
T133	0	4	0	0
T136	0	4	0	0
T150	0	30	0	0
T151	0	249	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	1612	0	0
T5	197082	0	0	0
T10	261666	0	0	0
T12	173067	21	0	0
T17	2126	0	0	0
T22	4131	0	0	0
T34	136608	0	0	0
T41	0	19	0	0
T75	119373	0	0	0
T90	2444	0	0	0
T104	1738	0	0	0
T105	4239	0	0	0
T106	0	11	0	0
T107	0	6	0	0
T128	0	110	0	0
T129	0	78	0	0
T133	0	10	0	0
T136	0	13	0	0
T150	0	32	0	0
T151	0	224	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	1563	0	0
T5	197082	0	0	0
T10	261666	0	0	0
T12	173067	25	0	0
T17	2126	0	0	0
T22	4131	0	0	0
T34	136608	0	0	0
T41	0	13	0	0
T75	119373	0	0	0
T90	2444	0	0	0
T104	1738	0	0	0
T105	4239	0	0	0
T106	0	1	0	0
T107	0	29	0	0
T128	0	92	0	0
T129	0	76	0	0
T133	0	9	0	0
T136	0	6	0	0
T150	0	3	0	0
T151	0	216	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	1592	0	0
T5	197082	0	0	0
T10	261666	0	0	0
T12	173067	16	0	0
T17	2126	0	0	0
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T34	136608	0	0	0
T41	0	17	0	0
T75	119373	0	0	0
T90	2444	0	0	0
T104	1738	0	0	0
T105	4239	0	0	0
T106	0	5	0	0
T107	0	15	0	0
T128	0	75	0	0
T129	0	76	0	0
T133	0	9	0	0
T136	0	4	0	0
T150	0	15	0	0
T151	0	218	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	1528	0	0
T5	197082	0	0	0
T10	261666	0	0	0
T12	173067	28	0	0
T17	2126	0	0	0
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T41	0	11	0	0
T75	119373	0	0	0
T90	2444	0	0	0
T104	1738	0	0	0
T105	4239	0	0	0
T106	0	7	0	0
T107	0	26	0	0
T128	0	48	0	0
T129	0	71	0	0
T133	0	6	0	0
T136	0	12	0	0
T150	0	33	0	0
T151	0	210	0	0