Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	190054	0	0
entropy_period_rd_A	2147483647	2054	0	0
intr_enable_rd_A	2147483647	2960	0	0
prefix_0_rd_A	2147483647	2543	0	0
prefix_10_rd_A	2147483647	2445	0	0
prefix_1_rd_A	2147483647	2384	0	0
prefix_2_rd_A	2147483647	2363	0	0
prefix_3_rd_A	2147483647	2431	0	0
prefix_4_rd_A	2147483647	2371	0	0
prefix_5_rd_A	2147483647	2422	0	0
prefix_6_rd_A	2147483647	2464	0	0
prefix_7_rd_A	2147483647	2478	0	0
prefix_8_rd_A	2147483647	2424	0	0
prefix_9_rd_A	2147483647	2441	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	190054	0	0
T49	605333	54273	0	0
T50	0	132110	0	0
T60	509549	0	0	0
T61	182338	0	0	0
T71	103577	0	0	0
T112	0	297	0	0
T115	781584	0	0	0
T116	0	2	0	0
T118	0	1	0	0
T123	0	67	0	0
T125	0	191	0	0
T126	0	105	0	0
T130	0	3	0	0
T131	0	6	0	0
T133	193974	0	0	0
T134	108344	0	0	0
T135	8430	0	0	0
T136	12456	0	0	0
T137	208747	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2054	0	0
T87	5558	16	0	0
T116	27466	97	0	0
T131	7265	21	0	0
T154	9717	49	0	0
T155	6568	19	0	0
T156	7974	15	0	0
T157	11615	75	0	0
T158	73018	135	0	0
T159	1820	13	0	0
T160	5629	27	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2960	0	0
T87	5558	24	0	0
T116	27466	147	0	0
T131	7265	8	0	0
T154	9717	8	0	0
T155	6568	11	0	0
T156	7974	26	0	0
T157	11615	52	0	0
T158	73018	244	0	0
T159	1820	4	0	0
T160	5629	34	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2543	0	0
T87	5558	17	0	0
T92	2792	2	0	0
T116	27466	71	0	0
T131	7265	9	0	0
T154	9717	28	0	0
T155	6568	7	0	0
T156	7974	25	0	0
T157	11615	63	0	0
T158	73018	241	0	0
T159	1820	8	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2445	0	0
T87	5558	16	0	0
T92	2792	4	0	0
T116	27466	82	0	0
T131	7265	12	0	0
T154	9717	46	0	0
T155	6568	45	0	0
T156	7974	11	0	0
T157	11615	47	0	0
T158	73018	239	0	0
T159	1820	6	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2384	0	0
T87	5558	30	0	0
T92	2792	1	0	0
T116	27466	80	0	0
T131	7265	3	0	0
T154	9717	19	0	0
T155	6568	26	0	0
T156	7974	21	0	0
T157	11615	22	0	0
T158	73018	267	0	0
T160	5629	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2363	0	0
T87	5558	20	0	0
T92	2792	7	0	0
T116	27466	90	0	0
T131	7265	14	0	0
T154	9717	28	0	0
T155	6568	29	0	0
T156	7974	15	0	0
T157	11615	12	0	0
T158	73018	228	0	0
T159	1820	1	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2431	0	0
T87	5558	9	0	0
T92	2792	9	0	0
T116	27466	108	0	0
T131	7265	4	0	0
T154	9717	27	0	0
T155	6568	10	0	0
T156	7974	15	0	0
T157	11615	25	0	0
T158	73018	220	0	0
T159	1820	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2371	0	0
T87	5558	29	0	0
T116	27466	86	0	0
T131	7265	4	0	0
T154	9717	19	0	0
T155	6568	26	0	0
T156	7974	11	0	0
T157	11615	30	0	0
T158	73018	205	0	0
T159	1820	2	0	0
T160	5629	16	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2422	0	0
T87	5558	12	0	0
T116	27466	73	0	0
T131	7265	2	0	0
T154	9717	25	0	0
T155	6568	21	0	0
T156	7974	18	0	0
T157	11615	19	0	0
T158	73018	240	0	0
T159	1820	5	0	0
T160	5629	43	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2464	0	0
T87	5558	26	0	0
T116	27466	94	0	0
T131	7265	13	0	0
T154	9717	24	0	0
T155	6568	13	0	0
T156	7974	23	0	0
T157	11615	53	0	0
T158	73018	260	0	0
T159	1820	4	0	0
T160	5629	15	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2478	0	0
T87	5558	26	0	0
T116	27466	54	0	0
T131	7265	5	0	0
T154	9717	57	0	0
T155	6568	26	0	0
T156	7974	12	0	0
T157	11615	26	0	0
T158	73018	261	0	0
T159	1820	7	0	0
T160	5629	13	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2424	0	0
T87	5558	24	0	0
T116	27466	59	0	0
T131	7265	6	0	0
T154	9717	17	0	0
T155	6568	31	0	0
T156	7974	20	0	0
T157	11615	57	0	0
T158	73018	198	0	0
T159	1820	3	0	0
T160	5629	16	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2441	0	0
T87	5558	6	0	0
T116	27466	66	0	0
T131	7265	14	0	0
T154	9717	18	0	0
T155	6568	26	0	0
T156	7974	8	0	0
T157	11615	82	0	0
T158	73018	235	0	0
T160	5629	24	0	0
T161	6315	8	0	0