KMAC/UNMASKED Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: `3df77bec1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.073m	33.473ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.150s	33.804us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.130s	57.625us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.170s	6.431ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.590s	1.139ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.170s	502.573us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.130s	57.625us	20	20	100.00
		kmac_csr_aliasing	11.590s	1.139ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.720s	13.440us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.310s	242.480us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.354m	1.754s	50	50	100.00
V2	burst_write	kmac_burst_write	14.854m	90.229ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.263m	545.636ms	50	50	100.00
		kmac_test_vectors_sha3_256	31.358m	92.692ms	50	50	100.00
		kmac_test_vectors_sha3_384	29.291m	1.394s	50	50	100.00
		kmac_test_vectors_sha3_512	16.803m	270.405ms	50	50	100.00
		kmac_test_vectors_shake_128	1.593h	1.994s	50	50	100.00
		kmac_test_vectors_shake_256	1.309h	863.068ms	50	50	100.00
		kmac_test_vectors_kmac	5.570s	1.952ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.740s	3.905ms	50	50	100.00
V2	sideload	kmac_sideload	7.492m	200.000ms	49	50	98.00
V2	app	kmac_app	4.786m	43.918ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.368m	6.780ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	5.299m	189.013ms	50	50	100.00
V2	error	kmac_error	8.449m	40.392ms	50	50	100.00
V2	key_error	kmac_key_error	8.390s	8.198ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.110s	8.825ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.000s	15.855ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.305m	49.130ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	26.240s	594.943us	50	50	100.00
V2	stress_all	kmac_stress_all	36.432m	400.497ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.860s	29.488us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	308.372us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.610s	1.415ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.610s	1.415ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.150s	33.804us	5	5	100.00
		kmac_csr_rw	1.130s	57.625us	20	20	100.00
		kmac_csr_aliasing	11.590s	1.139ms	5	5	100.00
		kmac_same_csr_outstanding	2.790s	232.269us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.150s	33.804us	5	5	100.00
		kmac_csr_rw	1.130s	57.625us	20	20	100.00
		kmac_csr_aliasing	11.590s	1.139ms	5	5	100.00
		kmac_same_csr_outstanding	2.790s	232.269us	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.850s	539.573us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.850s	539.573us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.850s	539.573us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.850s	539.573us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.590s	965.672us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.291m	22.864ms	5	5	100.00
		kmac_tl_intg_err	6.310s	2.998ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.310s	2.998ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	26.240s	594.943us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.073m	33.473ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.492m	200.000ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.850s	539.573us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.291m	22.864ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.291m	22.864ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.291m	22.864ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.073m	33.473ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	26.240s	594.943us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.291m	22.864ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.000m	42.009ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.073m	33.473ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	57.723m	440.669ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			1274	1290	98.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.17	96.65	92.52	100.00	86.36	94.67	98.82	97.16

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 13 failures:

Test kmac_stress_all_with_rand_reset has 13 failures.

2.kmac_stress_all_with_rand_reset.1243467782
Line 627, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 52032919463 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 52032919463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_stress_all_with_rand_reset.336264442
Line 997, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 95188465587 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 95188465587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 6.kmac_app_with_partial_data.1611118718
    Line 359, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 9320709953 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (120 [0x78] vs 34 [0x22]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9320709953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1340) [scoreboard] Check failed digest_share*.size() == output_len_bytes (* [*] vs * [*]) Calculated output length(32) doesn't match actual output length(48)! has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 27.kmac_stress_all.585338951
    Line 425, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 63047089919 ps: (kmac_scoreboard.sv:1340) [uvm_test_top.env.scoreboard] Check failed digest_share0.size() == output_len_bytes (48 [0x30] vs 32 [0x20]) Calculated output length(32) doesn't match actual output length(48)!
  UVM_INFO @ 63047089919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_sideload has 1 failures.
  - 45.kmac_sideload.1028853986
    Line 405, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```