Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	50855	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118688

1

T1

12

T2

45

T3

193

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	97065	1			T1	20		T2	62		T3	134
values[0x0]	34964	1			T1	6		T2	35		T3	57
values[0x1]	37514	1			T1	14		T2	57		T3	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37319	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

132224

1

T1

14

T2

86

T3

213

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	719	1			T4	2		T5	3		T12	18
valid_sources[0x01]	869	1			T4	5		T5	6		T12	4
valid_sources[0x02]	1130	1			T4	6		T5	2		T6	108
valid_sources[0x03]	753	1			T3	2		T4	4		T5	5
valid_sources[0x04]	548	1			T3	2		T4	6		T5	11
valid_sources[0x05]	864	1			T1	1		T4	6		T5	2
valid_sources[0x06]	918	1			T2	2		T4	4		T5	6
valid_sources[0x07]	587	1			T4	6		T5	7		T12	10
valid_sources[0x08]	847	1			T2	1		T4	3		T5	5
valid_sources[0x09]	410	1			T2	4		T3	6		T4	8
valid_sources[0x0a]	675	1			T2	2		T4	7		T5	6
valid_sources[0x0b]	600	1			T2	2		T4	4		T5	4
valid_sources[0x0c]	781	1			T4	5		T5	4		T12	4
valid_sources[0x0d]	552	1			T1	1		T4	4		T5	8
valid_sources[0x0e]	568	1			T4	9		T5	5		T12	2
valid_sources[0x0f]	757	1			T4	12		T5	7		T13	2
valid_sources[0x10]	683	1			T4	6		T5	6		T25	5
valid_sources[0x11]	585	1			T3	1		T4	8		T5	3
valid_sources[0x12]	600	1			T4	5		T5	3		T12	2
valid_sources[0x13]	569	1			T4	2		T5	4		T12	3
valid_sources[0x14]	933	1			T2	1		T3	14		T4	7
valid_sources[0x15]	929	1			T1	1		T4	7		T5	6
valid_sources[0x16]	1177	1			T4	3		T5	4		T25	3
valid_sources[0x17]	511	1			T4	4		T5	6		T12	1
valid_sources[0x18]	668	1			T4	9		T5	6		T25	4
valid_sources[0x19]	462	1			T3	3		T4	10		T5	4
valid_sources[0x1a]	492	1			T2	1		T4	6		T5	5
valid_sources[0x1b]	640	1			T4	10		T5	9		T7	1
valid_sources[0x1c]	676	1			T2	1		T4	9		T5	10
valid_sources[0x1d]	564	1			T4	9		T5	3		T25	2
valid_sources[0x1e]	691	1			T4	5		T5	2		T12	4
valid_sources[0x1f]	706	1			T1	1		T4	6		T5	3
valid_sources[0x20]	565	1			T3	4		T4	8		T5	4
valid_sources[0x21]	540	1			T1	1		T4	7		T5	2
valid_sources[0x22]	752	1			T2	1		T3	2		T4	5
valid_sources[0x23]	511	1			T4	6		T5	8		T12	1
valid_sources[0x24]	460	1			T4	5		T5	3		T25	3
valid_sources[0x25]	389	1			T2	2		T4	4		T5	7
valid_sources[0x26]	606	1			T1	1		T4	3		T5	5
valid_sources[0x27]	767	1			T4	10		T5	4		T12	9
valid_sources[0x28]	689	1			T2	1		T3	1		T4	5
valid_sources[0x29]	800	1			T4	2		T5	3		T13	17
valid_sources[0x2a]	977	1			T2	3		T3	5		T4	10
valid_sources[0x2b]	587	1			T2	1		T4	8		T5	2
valid_sources[0x2c]	571	1			T4	2		T5	6		T6	54
valid_sources[0x2d]	506	1			T4	4		T5	9		T13	14
valid_sources[0x2e]	657	1			T2	1		T4	2		T5	10
valid_sources[0x2f]	626	1			T2	3		T4	8		T5	6
valid_sources[0x30]	503	1			T2	2		T4	7		T5	7
valid_sources[0x31]	752	1			T1	1		T3	5		T4	6
valid_sources[0x32]	515	1			T4	5		T5	3		T7	3
valid_sources[0x33]	467	1			T4	5		T12	3		T13	30
valid_sources[0x34]	710	1			T3	4		T4	7		T5	9
valid_sources[0x35]	598	1			T4	9		T5	5		T12	7
valid_sources[0x36]	651	1			T2	2		T4	2		T5	5
valid_sources[0x37]	544	1			T3	2		T4	10		T5	10
valid_sources[0x38]	675	1			T3	1		T4	2		T5	2
valid_sources[0x39]	877	1			T4	2		T5	2		T7	7
valid_sources[0x3a]	671	1			T1	1		T4	6		T5	3
valid_sources[0x3b]	470	1			T1	1		T2	1		T3	3
valid_sources[0x3c]	574	1			T2	1		T4	5		T5	7
valid_sources[0x3d]	985	1			T4	6		T5	5		T6	205
valid_sources[0x3e]	635	1			T4	5		T5	7		T13	8
valid_sources[0x3f]	452	1			T4	2		T5	2		T12	2
valid_sources[0x40]	512	1			T3	3		T4	11		T5	5
valid_sources[0x41]	618	1			T4	6		T5	5		T25	4
valid_sources[0x42]	800	1			T4	2		T5	3		T7	1
valid_sources[0x43]	513	1			T3	4		T4	6		T5	2
valid_sources[0x44]	391	1			T4	9		T5	5		T12	4
valid_sources[0x45]	462	1			T4	7		T5	6		T12	5
valid_sources[0x46]	635	1			T2	2		T3	5		T4	4
valid_sources[0x47]	923	1			T4	12		T5	6		T13	28
valid_sources[0x48]	597	1			T4	9		T5	8		T12	6
valid_sources[0x49]	739	1			T2	1		T4	8		T5	6
valid_sources[0x4a]	718	1			T3	1		T4	2		T5	4
valid_sources[0x4b]	695	1			T4	4		T5	6		T12	1
valid_sources[0x4c]	875	1			T4	5		T5	6		T7	2
valid_sources[0x4d]	834	1			T4	8		T5	7		T12	5
valid_sources[0x4e]	783	1			T4	2		T5	4		T25	1
valid_sources[0x4f]	726	1			T2	1		T3	1		T4	2
valid_sources[0x50]	896	1			T4	5		T5	6		T12	6
valid_sources[0x51]	694	1			T1	1		T4	10		T5	5
valid_sources[0x52]	612	1			T1	1		T2	2		T4	8
valid_sources[0x53]	627	1			T3	9		T4	6		T5	7
valid_sources[0x54]	661	1			T4	1		T5	8		T12	1
valid_sources[0x55]	694	1			T3	2		T4	4		T5	6
valid_sources[0x56]	653	1			T4	6		T5	10		T12	2
valid_sources[0x57]	835	1			T4	3		T5	4		T7	1
valid_sources[0x58]	640	1			T4	4		T5	7		T25	2
valid_sources[0x59]	461	1			T4	4		T5	3		T12	3
valid_sources[0x5a]	1219	1			T3	7		T4	3		T5	5
valid_sources[0x5b]	717	1			T2	1		T3	4		T4	4
valid_sources[0x5c]	653	1			T1	1		T4	3		T5	11
valid_sources[0x5d]	516	1			T4	5		T5	3		T13	43
valid_sources[0x5e]	791	1			T3	13		T4	6		T5	3
valid_sources[0x5f]	655	1			T4	5		T5	7		T13	12
valid_sources[0x60]	770	1			T4	10		T5	8		T12	7
valid_sources[0x61]	581	1			T3	3		T4	1		T5	8
valid_sources[0x62]	572	1			T2	2		T4	5		T5	5
valid_sources[0x63]	660	1			T4	5		T5	2		T25	4
valid_sources[0x64]	618	1			T2	1		T4	10		T5	6
valid_sources[0x65]	383	1			T4	5		T5	11		T12	2
valid_sources[0x66]	552	1			T4	4		T5	4		T12	4
valid_sources[0x67]	480	1			T3	1		T4	3		T5	2
valid_sources[0x68]	685	1			T1	1		T3	6		T4	13
valid_sources[0x69]	434	1			T3	1		T4	4		T5	1
valid_sources[0x6a]	641	1			T2	2		T4	12		T5	3
valid_sources[0x6b]	522	1			T4	7		T5	5		T13	20
valid_sources[0x6c]	891	1			T2	3		T5	3		T13	37
valid_sources[0x6d]	571	1			T1	1		T2	6		T4	5
valid_sources[0x6e]	530	1			T4	5		T5	5		T12	1
valid_sources[0x6f]	549	1			T4	3		T5	3		T7	1
valid_sources[0x70]	554	1			T4	8		T5	8		T12	1
valid_sources[0x71]	505	1			T2	2		T3	4		T4	8
valid_sources[0x72]	766	1			T4	5		T5	2		T7	4
valid_sources[0x73]	720	1			T3	1		T4	12		T26	60
valid_sources[0x74]	423	1			T3	1		T4	3		T5	5
valid_sources[0x75]	682	1			T4	9		T5	4		T13	18
valid_sources[0x76]	874	1			T4	5		T5	4		T13	19
valid_sources[0x77]	786	1			T1	1		T4	3		T5	10
valid_sources[0x78]	520	1			T2	3		T3	2		T4	3
valid_sources[0x79]	716	1			T4	8		T5	6		T13	12
valid_sources[0x7a]	525	1			T4	3		T5	9		T12	3
valid_sources[0x7b]	642	1			T4	4		T5	5		T25	2
valid_sources[0x7c]	897	1			T2	2		T3	1		T4	7
valid_sources[0x7d]	599	1			T1	1		T4	10		T5	10
valid_sources[0x7e]	485	1			T4	8		T5	3		T13	31
valid_sources[0x7f]	728	1			T2	1		T4	7		T5	8
valid_sources[0x80]	608	1			T4	6		T5	7		T12	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

56159

1

T1

9

T2

33

T3

82

values[0x0]

all_enables

biggest_size

31669

1

T1

2

T2

5

T3

52

values[0x1]

all_enables

biggest_size

30860

1

T1

1

T2

7

T3

59