Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

64785

1

T1

28

T2

109

T3

61

full_word

119607

1

T1

12

T2

45

T3

193

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	184102	1			T1	40		T2	154		T3	254
auto[TlIntgErrCmd]	93	1			T5	2		T13	4		T31	2
auto[TlIntgErrData]	91	1			T5	5		T13	10		T31	1
auto[TlIntgErrBoth]	106	1			T5	3		T13	6		T31	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99588

1

T1

20

T2

62

T3

134

auto[1]

84804

1

T1

20

T2

92

T3

120

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	43084	1			T1	11		T2	29		T3	52
auto[TlIntgErrNone]	partial	auto[1]	21431	1			T1	17		T2	80		T3	9
auto[TlIntgErrNone]	full_word	auto[0]	56376	1			T1	9		T2	33		T3	82
auto[TlIntgErrNone]	full_word	auto[1]	63211	1			T1	3		T2	12		T3	111
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T5	1		T13	1		T33	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T5	1		T13	3		T31	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T32	1		T88	1		T89	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T86	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	36	1			T5	1		T13	4		T32	2
auto[TlIntgErrData]	partial	auto[1]	52	1			T5	4		T13	5		T31	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T13	1		T90	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	1	1			T55	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T5	1		T13	2		T31	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T5	1		T13	3		T31	5
auto[TlIntgErrBoth]	full_word	auto[0]	9	1			T5	1		T13	1		T30	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T33	1		T86	1		T91	1