Unified Coverage Report :: Module :: prim_subreg_shadow

Module : prim_subreg_shadow

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_cfg_shadowed_kmac_en	97.12	100.00	88.46			100.00	100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength	97.12	100.00	88.46			100.00	100.00
tb.dut.u_reg.u_cfg_shadowed_mode	97.12	100.00	88.46			100.00	100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness	97.12	100.00	88.46			100.00	100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness	97.12	100.00	88.46			100.00	100.00
tb.dut.u_reg.u_cfg_shadowed_sideload	97.12	100.00	88.46			100.00	100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode	97.12	100.00	88.46			100.00	100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process	97.12	100.00	88.46			100.00	100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask	97.12	100.00	88.46			100.00	100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready	97.12	100.00	88.46			100.00	100.00
tb.dut.u_reg.u_cfg_shadowed_err_processed	97.12	100.00	88.46			100.00	100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength	97.12	100.00	88.46			100.00	100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed	97.12	100.00	88.46			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_cfg_shadowed_kmac_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	94.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.78	100.00	99.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_cfg_shadowed_kstrength

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	94.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.78	100.00	99.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_cfg_shadowed_mode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	94.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.78	100.00	99.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_cfg_shadowed_msg_endianness

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	94.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.78	100.00	99.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_cfg_shadowed_state_endianness

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	94.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.78	100.00	99.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_cfg_shadowed_sideload

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	94.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.78	100.00	99.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_mode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	94.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.78	100.00	99.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	94.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.78	100.00	99.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_cfg_shadowed_msg_mask

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	94.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.78	100.00	99.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_ready

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	94.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.78	100.00	99.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_cfg_shadowed_err_processed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	94.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.78	100.00	99.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	94.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.78	100.00	99.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_entropy_refresh_threshold_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	94.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.78	100.00	99.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_subreg_shadow

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Module : prim_subreg_shadow

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T25
1	0	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Covered	T2,T3,T4
1	1	0	1	Covered	T4,T6,T25
1	1	1	0	Not Covered
1	1	1	1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T6,T25

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T25

---

Branch Coverage for Module : prim_subreg_shadow

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_subreg_shadow

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	2795	2795	0	0
MubiIsNotYetSupported_A	16230838	15584192	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2795	2795	0	0
T1	13	13	0	0
T2	13	13	0	0
T3	13	13	0	0
T4	13	13	0	0
T5	13	13	0	0
T6	13	13	0	0
T7	13	13	0	0
T8	13	13	0	0
T12	13	13	0	0
T13	13	13	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16230838	15584192	0	0
T1	10400	9451	0	0
T2	20020	19149	0	0
T3	35295	34268	0	0
T4	88465	82524	0	0
T5	149552	137774	0	0
T6	62465	59657	0	0
T7	88218	86970	0	0
T8	15808	14911	0	0
T12	64142	63297	0	0
T13	125398	104598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kmac_en

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kmac_en

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T25,T27
1	0	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Covered	T2,T3,T4
1	1	0	1	Covered	T28,T62,T63
1	1	1	0	Not Covered
1	1	1	1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T25,T27

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T25,T27

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T25,T27
1	0	Covered	T4,T25,T27
1	1	Covered	T28,T62,T63

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T25,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kmac_en

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T25,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kmac_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	215	215	0	0
MubiIsNotYetSupported_A	1248526	1198784	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kstrength

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kstrength

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T25,T27
1	0	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Covered	T2,T3,T4
1	1	0	1	Covered	T4,T27,T28
1	1	1	0	Not Covered
1	1	1	1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T27,T28

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T25,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kstrength

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_kstrength

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	215	215	0	0
MubiIsNotYetSupported_A	1248526	1198784	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_mode

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_mode

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T25,T27
1	0	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Covered	T2,T3,T4
1	1	0	1	Covered	T28,T64,T65
1	1	1	0	Not Covered
1	1	1	1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T28,T64,T65

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T25,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_mode

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_mode

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	215	215	0	0
MubiIsNotYetSupported_A	1248526	1198784	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_endianness

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_endianness

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T25,T60
1	0	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Covered	T2,T3,T4
1	1	0	1	Covered	T27,T28,T65
1	1	1	0	Not Covered
1	1	1	1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T27,T28,T65

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T25,T60

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_endianness

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_endianness

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	215	215	0	0
MubiIsNotYetSupported_A	1248526	1198784	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_state_endianness

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_state_endianness

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T25,T27,T65
1	0	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Covered	T2,T3,T4
1	1	0	1	Covered	T27,T66,T67
1	1	1	0	Not Covered
1	1	1	1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T27,T66,T67

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T27,T65

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_state_endianness

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_state_endianness

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	215	215	0	0
MubiIsNotYetSupported_A	1248526	1198784	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_sideload

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_sideload

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T25,T27,T60
1	0	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Covered	T2,T3,T4
1	1	0	1	Covered	T27,T68,T66
1	1	1	0	Not Covered
1	1	1	1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T12,T13

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T12,T13

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T13
1	0	Covered	T5,T12,T13
1	1	Covered	T27,T68,T66

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T27,T60

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_sideload

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_sideload

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	215	215	0	0
MubiIsNotYetSupported_A	1248526	1198784	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_mode

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_mode

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T25,T27,T60
1	0	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Covered	T2,T3,T4
1	1	0	1	Covered	T64,T65,T68
1	1	1	0	Not Covered
1	1	1	1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T64,T65,T68

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T27,T60

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_mode

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_mode

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	215	215	0	0
MubiIsNotYetSupported_A	1248526	1198784	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T25,T27,T65
1	0	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Covered	T2,T3,T4
1	1	0	1	Covered	T27,T28,T65
1	1	1	0	Not Covered
1	1	1	1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T27,T28,T65

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T27,T65

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	215	215	0	0
MubiIsNotYetSupported_A	1248526	1198784	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_mask

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_mask

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T25,T27
1	0	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Covered	T2,T3,T4
1	1	0	1	Covered	T25,T27,T28
1	1	1	0	Not Covered
1	1	1	1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T12

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T12

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T12
1	0	Covered	T4,T5,T12
1	1	Covered	T25,T27,T28

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T25,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_mask

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_msg_mask

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	215	215	0	0
MubiIsNotYetSupported_A	1248526	1198784	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_ready

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_ready

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T25,T27
1	0	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Covered	T2,T3,T4
1	1	0	1	Covered	T27,T28,T65
1	1	1	0	Not Covered
1	1	1	1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T25,T27

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T25,T27

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T25,T27
1	0	Covered	T4,T25,T27
1	1	Covered	T27,T28,T65

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T25,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_ready

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T25,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_entropy_ready

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	215	215	0	0
MubiIsNotYetSupported_A	1248526	1198784	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_err_processed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_err_processed

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T27,T65
1	0	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Covered	T2,T3,T4
1	1	0	1	Covered	T28,T65,T69
1	1	1	0	Not Covered
1	1	1	1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T28,T65,T69

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T27,T65

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_err_processed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_err_processed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	215	215	0	0
MubiIsNotYetSupported_A	1248526	1198784	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

Line Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T28,T65
1	0	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Covered	T2,T3,T4
1	1	0	1	Covered	T27,T65,T68
1	1	1	0	Not Covered
1	1	1	1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T4
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T27,T28

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T27,T28

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T28
1	0	Covered	T4,T27,T28
1	1	Covered	T27,T65,T68

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T28,T65

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T27,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	215	215	0	0
MubiIsNotYetSupported_A	1248526	1198784	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

Line Coverage for Instance : tb.dut.u_reg.u_entropy_refresh_threshold_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
			MISSING_ELSE
113	1	1
114		unreachable
138	1	1
139		unreachable
160	1	1
161		unreachable
180	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_entropy_refresh_threshold_shadowed

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T24
1	0	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T3,T4,T5
1	0	1	1	Covered	T3,T4,T5
1	1	0	1	Covered	T4,T6,T24
1	1	1	0	Not Covered
1	1	1	1	Covered	T3,T4,T5

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T3,T4,T5
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T6,T24

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T24

---

Branch Coverage for Instance : tb.dut.u_reg.u_entropy_refresh_threshold_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	183	(((~staged_q) != wr_data)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	if ((!rst_ni))
-2-:	102	if ((wr_en && (!err_storage)))
-3-:	104	if ((phase_clear || err_storage))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_entropy_refresh_threshold_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	215	215	0	0
MubiIsNotYetSupported_A	1248526	1198784	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0