Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1248526	16292	0	0
DepthKnown_A	1248526	1198784	0	0
RvalidKnown_A	1248526	1198784	0	0
WreadyKnown_A	1248526	1198784	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	16292	0	0
T2	1540	171	0	0
T3	2715	0	0	0
T4	6805	0	0	0
T5	11504	0	0	0
T6	4805	0	0	0
T7	6786	317	0	0
T8	1216	0	0	0
T12	4934	0	0	0
T13	9646	0	0	0
T14	0	1015	0	0
T15	0	478	0	0
T16	0	190	0	0
T17	0	826	0	0
T18	0	397	0	0
T19	0	482	0	0
T20	0	313	0	0
T21	0	118	0	0
T24	7542	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1248526	18808	0	0
DepthKnown_A	1248526	1198784	0	0
RvalidKnown_A	1248526	1198784	0	0
WreadyKnown_A	1248526	1198784	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	18808	0	0
T2	1540	87	0	0
T3	2715	0	0	0
T4	6805	0	0	0
T5	11504	0	0	0
T6	4805	0	0	0
T7	6786	308	0	0
T8	1216	0	0	0
T12	4934	0	0	0
T13	9646	0	0	0
T14	0	558	0	0
T15	0	255	0	0
T16	0	403	0	0
T17	0	478	0	0
T18	0	1429	0	0
T19	0	261	0	0
T20	0	610	0	0
T21	0	110	0	0
T24	7542	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1248526	266563	0	0
DepthKnown_A	1248526	1198784	0	0
RvalidKnown_A	1248526	1198784	0	0
WreadyKnown_A	1248526	1198784	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	266563	0	0
T1	800	40	0	0
T2	1540	127	0	0
T3	2715	273	0	0
T4	6805	2959	0	0
T5	11504	2596	0	0
T6	4805	773	0	0
T7	6786	593	0	0
T8	1216	22	0	0
T12	4934	731	0	0
T13	9646	5244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1248526	318440	0	0
DepthKnown_A	1248526	1198784	0	0
RvalidKnown_A	1248526	1198784	0	0
WreadyKnown_A	1248526	1198784	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	318440	0	0
T1	800	40	0	0
T2	1540	67	0	0
T3	2715	254	0	0
T4	6805	1436	0	0
T5	11504	1332	0	0
T6	4805	621	0	0
T7	6786	567	0	0
T8	1216	22	0	0
T12	4934	685	0	0
T13	9646	2685	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1248526	1198784	0	0
T1	800	727	0	0
T2	1540	1473	0	0
T3	2715	2636	0	0
T4	6805	6348	0	0
T5	11504	10598	0	0
T6	4805	4589	0	0
T7	6786	6690	0	0
T8	1216	1147	0	0
T12	4934	4869	0	0
T13	9646	8046	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0