Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.77	96.32	91.89	63.67	100.00	92.73	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	96.82	96.32	91.89	100.00	100.00	92.73	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.82	96.32	91.89	100.00	100.00	92.73	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.01	96.58	92.46	100.00	87.50	94.67	98.84

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
intr_fifo_empty	93.75	100.00	75.00			100.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	93.01	94.07	89.80		88.24	92.94	100.00
u_errchk	95.99	97.14	96.67		90.00	96.15	100.00
u_kmac_core	93.72	98.75	92.86	100.00	87.50	92.31	90.91
u_msgfifo	97.55	100.00	94.00		100.00	93.75	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.98	99.35	96.63	100.00		98.94	100.00
u_sha3	92.14	93.81	86.84	100.00	80.56	91.62	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.69	89.64	80.83			88.30	100.00
u_tlul_adapter_msgfifo	79.67	86.78	73.83			76.83	81.25

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		163	157	96.32
ALWAYS	346	0	0
ALWAYS	346	2	2	100.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
ALWAYS	429	9	9	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
ALWAYS	488	6	6	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	539	0	0
CONT_ASSIGN	541	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
ALWAYS	563	5	5	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	582	1	1	100.00
CONT_ASSIGN	592	1	1	100.00
ALWAYS	612	3	3	100.00
CONT_ASSIGN	616	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	643	7	5	71.43
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	684	1	0	0.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
ALWAYS	721	3	3	100.00
ALWAYS	725	28	28	100.00
CONT_ASSIGN	875	1	1	100.00
CONT_ASSIGN	878	1	1	100.00
CONT_ASSIGN	942	1	1	100.00
CONT_ASSIGN	944	1	1	100.00
CONT_ASSIGN	974	1	1	100.00
CONT_ASSIGN	979	1	1	100.00
CONT_ASSIGN	980	1	1	100.00
CONT_ASSIGN	982	1	1	100.00
CONT_ASSIGN	985	0	0
ALWAYS	1103	0	0
ALWAYS	1103	2	2	100.00
CONT_ASSIGN	1255	1	0	0.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1257	1	1	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
CONT_ASSIGN	1357	1	1	100.00
ALWAYS	1363	6	5	83.33
CONT_ASSIGN	1372	1	1	100.00
CONT_ASSIGN	1374	1	1	100.00
ALWAYS	1386	4	4	100.00
CONT_ASSIGN	1392	1	1	100.00
ALWAYS	1415	4	4	100.00
ALWAYS	1425	3	3	100.00
CONT_ASSIGN	1436	1	1	100.00
CONT_ASSIGN	1440	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
346	1	1
347	1	1
352	0	1
421	1	1
422	1	1
426	1	1
429	1	1
430	1	1
431	1	1
432	1	1
434	1	1
436	1	1
440	1	1
444	1	1
448	1	1
464	1	1
465	1	1
466	1	1
469	1	1
473	1	1
474	1	1
478	1	1
481	1	1
488	1	1
489	1	1
490	1	1
491	1	1
492	1	1
493	1	1
			MISSING_ELSE
			MISSING_ELSE
513	1	1
518	1	1
525	1	1
528	1	1
529	1	1
530	1	1
533	5	5
534	5	5
537	1	1
539		unreachable
541	1	1
545	1	1
547	1	1
548	1	1
551	1	1
552	1	1
555	1	1
563	1	1
564	1	1
565	1	1
566	1	1
568	1	1
573	1	1
580	1	1
581	1	1
582	1	1
592	1	1
612	2	2
613	1	1
616	1	1
635	1	1
640	1	1
643	1	1
645	1	1
650	1	1
654	1	1
658	1	1
662	0	1
666	0	1
679	1	1
684	0	1
691	1	1
701	1	1
721	3	3
725	1	1
727	1	1
728	1	1
730	1	1
732	1	1
734	1	1
735	1	1
738	1	1
741	1	1
747	1	1
748	1	1
750	1	1
755	1	1
756	1	1
757	1	1
759	1	1
765	1	1
770	1	1
771	1	1
773	1	1
775	1	1
781	1	1
782	1	1
784	1	1
790	1	1
791	1	1
803	1	1
804	1	1
			MISSING_ELSE
875	1	1
878	1	1
942	1	1
944	1	1
974	1	1
979	1	1
980	1	1
982	1	1
985		unreachable
1103	1	1
1104	1	1
1255	0	1
1256	1	1
1257	1	1
1266	1	1
1272	1	1
1273	1	1
1274	1	1
1275	1	1
1278	1	1
1287	1	1
1331	1	1
1345	1	1
1352	1	1
1357	1	1
1363	1	1
1364	1	1
1365	1	1
1366	0	1
1367	1	1
1368	1	1
			MISSING_ELSE
1372	1	1
1374	1	1
1386	1	1
1387	1	1
1388	1	1
1389	1	1
			MISSING_ELSE
1392	1	1
1415	1	1
1416	1	1
1417	1	1
1419	1	1
			MISSING_ELSE
1425	1	1
1426	1	1
1429	1	1
1436	1	1
1440	1	1
1442	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	74	68	91.89
Logical	74	68	91.89
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T28,T26,T53

 LINE       541
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T28,T26,T53

 LINE       545
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T35,T37,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       552
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       565
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       565
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       565
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T4,T5,T6
1	-	Covered	T4,T5,T6

 LINE       573
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       616
 EXPRESSION (((~msgfifo_empty_q)) & msgfifo_empty)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       635
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T4,T5,T6
0	0	0	1	Covered	T45,T31,T54
0	0	1	0	Not Covered
0	1	0	0	Covered	T7,T8,T9
1	0	0	0	Covered	T25,T26,T27

 LINE       679
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T4,T5,T6
0	0	0	1	Not Covered
0	0	1	0	Covered	T10,T11,T12
0	1	0	0	Unreachable
1	0	0	0	Covered	T10,T11,T12

 LINE       691
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T4,T5,T6
0	0	0	0	0	1	Covered	T10,T11,T12
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T10,T11,T12
0	0	1	0	0	0	Covered	T10,T11,T12
0	1	0	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	0	Covered	T10,T11,T12

 LINE       732
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       734
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T16

 LINE       748
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T6,T17,T19
1	Covered	T5,T6,T16

 LINE       974
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       1104
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       1345
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T55,T56,T57
1	0	Covered	T4,T5,T6
1	1	Covered	T55,T56,T57

 LINE       1345
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T55,T56,T57
1	0	Covered	T4,T5,T6
1	1	Covered	T55,T56,T57

 LINE       1374
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T4,T5,T6
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T10,T11,T12
0	0	1	0	0	Covered	T7,T8,T9
0	1	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	64	90.14
Total Bits	6534	4160	63.67
Total Bits 0->1	3267	2080	63.67
Total Bits 1->0	3267	2080	63.67

Ports	71	64	90.14
Port Bits	6534	4160	63.67
Port Bits 0->1	3267	2080	63.67
Port Bits 1->0	3267	2080	63.67

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T58	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T2,T58	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T58	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T58	Yes	T2,T3,T58	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T58	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T58	Yes	T2,T3,T58	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T2,T3,T58	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T2,T58,T59	Yes	T2,T58,T59	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T2,T3,T58	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T58	Yes	T1,T2,T58	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T58	Yes	T1,T2,T58	OUTPUT
keymgr_key_i.key[0][0]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][1]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][3:2]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][4]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][7:5]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][11:8]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][13:12]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][14]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][15]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][16]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][17]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][18]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][19]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][20]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][21]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][23:22]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][24]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][27:25]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][28]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][29]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][30]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][33:31]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][34]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][35]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][36]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][37]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][40:38]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][41]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][42]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][43]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][44]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][45]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][47:46]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][48]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][49]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][50]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][51]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][52]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][53]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][56:54]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][57]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][58]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][59]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][60]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][61]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][62]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][63]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][64]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][65]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][67:66]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][68]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][69]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][70]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][74:71]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][75]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][77:76]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][78]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][79]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][80]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][81]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][82]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][83]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][86:84]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][87]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][88]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][90:89]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][92:91]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][93]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][94]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][97:95]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][98]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][100:99]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][101]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][102]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][104:103]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][105]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][106]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][109:107]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][110]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][111]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][112]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][113]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][114]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][116:115]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][117]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][118]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][120:119]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][122:121]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][126:123]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][127]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][129:128]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][130]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][131]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][133:132]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][134]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][136:135]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][137]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][138]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][140:139]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][141]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][142]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][143]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][144]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][145]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][146]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][147]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][148]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][149]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][150]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][151]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][152]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][155:153]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][156]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][157]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][158]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][159]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][160]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][163:161]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][165:164]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][166]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][167]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][168]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][169]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][170]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][173:171]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][174]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][175]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][176]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][177]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][180:178]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][181]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][182]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][184:183]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][192:185]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][193]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][195:194]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][196]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][197]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][198]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][199]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][200]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][208:201]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][209]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][210]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][212:211]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][213]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][214]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][215]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][216]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][217]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][218]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][219]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][220]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][221]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][222]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][223]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][224]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][226:225]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][227]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][228]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][229]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][230]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][231]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][232]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][233]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][234]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][235]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][236]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][237]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][239:238]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][240]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][241]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][243:242]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][244]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][246:245]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][248:247]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][250:249]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][251]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][252]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][253]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][254]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][255]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][4:0]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][5]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][6]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][7]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][8]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][9]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][10]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][11]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][18:12]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][19]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][20]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][21]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][23:22]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][24]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][25]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][26]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][27]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][28]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][29]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][33:30]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][34]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][36:35]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][37]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][38]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][39]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][42:40]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][43]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][44]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][47:45]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][48]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][49]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][51:50]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][52]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][54:53]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][56:55]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][57]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][58]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][61:59]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][62]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][63]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][66:64]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][68:67]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][69]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][71:70]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][75:72]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][76]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][77]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][79:78]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][81:80]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][82]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][83]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][84]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][85]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][86]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][89:87]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][90]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][91]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][92]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][93]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][94]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][95]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][96]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][97]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][100:98]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][101]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][102]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][104:103]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][105]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][107:106]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][108]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][109]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][110]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][112:111]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][113]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][114]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][115]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][117:116]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][118]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][119]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][120]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][122:121]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][123]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][125:124]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][126]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][128:127]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][129]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][131:130]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][134:132]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][135]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][136]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][137]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][138]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][139]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][140]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][141]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][142]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][143]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][147:144]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][149:148]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][150]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][151]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][152]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][153]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][156:154]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][159:157]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][160]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][161]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][162]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][163]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][168:164]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][169]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][170]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][172:171]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][173]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][174]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][175]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][177:176]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][178]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][179]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][181:180]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][184:182]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][185]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][186]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][188:187]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][190:189]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][193:191]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][194]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][197:195]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][200:198]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][202:201]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][203]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][204]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][205]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][206]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][207]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][208]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][210:209]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][211]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][212]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][213]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][214]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][215]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][216]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][217]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][219:218]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][221:220]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][222]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][223]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][224]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][225]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][226]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][229:227]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][230]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][231]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][232]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][233]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][234]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][237:235]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][238]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][241:239]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][242]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][244:243]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][245]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][246]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][247]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][248]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][249]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][252:250]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][253]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][255:254]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.valid	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
app_i[0].last	Yes	Yes	T6,T19,T30	Yes	T6,T17,T19	INPUT
app_i[0].strb[7:0]	Yes	Yes	T6,T17,T30	Yes	T6,T17,T30	INPUT
app_i[0].data[63:0]	Yes	Yes	T6,T17,T19	Yes	T6,T17,T19	INPUT
app_i[0].valid	Yes	Yes	T6,T7,T17	Yes	T6,T7,T17	INPUT
app_i[1].last	Yes	Yes	T6,T19,T30	Yes	T6,T19,T30	INPUT
app_i[1].strb[7:0]	Yes	Yes	T6,T17,T30	Yes	T6,T17,T30	INPUT
app_i[1].data[63:0]	Yes	Yes	T6,T17,T19	Yes	T6,T17,T19	INPUT
app_i[1].valid	Yes	Yes	T6,T7,T17	Yes	T6,T7,T17	INPUT
app_i[2].last	Yes	Yes	T6,T19,T25	Yes	T6,T19,T29	INPUT
app_i[2].strb[7:0]	Yes	Yes	T6,T30,T36	Yes	T6,T30,T36	INPUT
app_i[2].data[63:0]	Yes	Yes	T6,T19,T29	Yes	T6,T19,T29	INPUT
app_i[2].valid	Yes	Yes	T6,T7,T19	Yes	T6,T7,T19	INPUT
app_o[0].error	Yes	Yes	T2,T60,T61	Yes	T2,T60,T61	OUTPUT
app_o[0].digest_share1[383:0]	No	No		No		OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T6,T19,T30	Yes	T6,T19,T30	OUTPUT
app_o[0].done	Yes	Yes	T6,T17,T19	Yes	T6,T17,T19	OUTPUT
app_o[0].ready	Yes	Yes	T6,T17,T19	Yes	T6,T17,T19	OUTPUT
app_o[1].error	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
app_o[1].digest_share1[383:0]	No	No		No		OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T6,T19,T30	Yes	T6,T19,T30	OUTPUT
app_o[1].done	Yes	Yes	T6,T19,T30	Yes	T6,T19,T30	OUTPUT
app_o[1].ready	Yes	Yes	T6,T17,T19	Yes	T6,T17,T19	OUTPUT
app_o[2].error	Yes	Yes	T25,T27,T39	Yes	T25,T27,T39	OUTPUT
app_o[2].digest_share1[383:0]	No	No		No		OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T6,T29,T30	Yes	T6,T29,T30	OUTPUT
app_o[2].done	Yes	Yes	T6,T19,T29	Yes	T6,T19,T29	OUTPUT
app_o[2].ready	Yes	Yes	T6,T19,T29	Yes	T6,T19,T29	OUTPUT
entropy_o.edn_req	No	No		No		OUTPUT
entropy_i.edn_bus[31:0]	No	No		No		INPUT
entropy_i.edn_fips	No	No		No		INPUT
entropy_i.edn_ack	No	No		No		INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
intr_kmac_done_o	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
intr_fifo_empty_o	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
intr_kmac_err_o	Yes	Yes	T2,T63,T66	Yes	T2,T63,T66	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T2,T60,T61	Yes	T2,T60,T61	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	773	Covered	T1
KmacIdle	741	Covered	T1
KmacKeyBlock	748	Covered	T1
KmacMsgFeed	738	Covered	T1
KmacPrefix	735	Covered	T1
KmacTerminalError	790	Covered	T1

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	782	Covered	T1
KmacDigest->KmacTerminalError	804	Covered	T1
KmacIdle->KmacMsgFeed	738	Covered	T1
KmacIdle->KmacPrefix	735	Covered	T1
KmacIdle->KmacTerminalError	804	Covered	T1
KmacKeyBlock->KmacMsgFeed	757	Covered	T1
KmacKeyBlock->KmacTerminalError	804	Covered	T1
KmacMsgFeed->KmacDigest	773	Covered	T1
KmacMsgFeed->KmacIdle	770	Covered	T1
KmacMsgFeed->KmacTerminalError	804	Covered	T1
KmacPrefix->KmacKeyBlock	748	Covered	T1
KmacPrefix->KmacMsgFeed	748	Covered	T1
KmacPrefix->KmacTerminalError	804	Covered	T1

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		55	51	92.73
TERNARY	426	2	2	100.00
CASE	434	6	5	83.33
IF	488	3	3	100.00
IF	563	3	3	100.00
IF	612	2	2	100.00
CASE	645	6	4	66.67
IF	721	2	2	100.00
CASE	730	15	15	100.00
IF	803	2	2	100.00
TERNARY	1104	2	2	100.00
IF	1363	4	3	75.00
IF	1386	3	3	100.00
IF	1415	3	3	100.00
IF	1425	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	426	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	434	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T4,T5,T6
CmdProcess	Covered	T4,T5,T6
CmdManualRun	Covered	T5,T6,T16
CmdDone	Covered	T4,T5,T6
CmdNone	Covered	T4,T5,T6
default	Not Covered

	LineNo.	Expression
-1-:	488	if ((!rst_ni))
-2-:	490	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	563	if ((!rst_ni))
-2-:	565	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	612	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	645	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T7,T8,T9
errchecker_err.valid	Covered	T45,T31,T54
sha3_err.valid	Covered	T25,T26,T27
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	721	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	730	case (kmac_st)
-2-:	732	if ((kmac_cmd == CmdStart))
-3-:	734	if ((CShake == app_sha3_mode))
-4-:	747	if (sha3_block_processed)
-5-:	748	(app_kmac_en) ? 
-6-:	756	if (sha3_block_processed)
-7-:	765	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	771	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	781	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T5,T6,T16
KmacIdle	1	0	-	-	-	-	-	-	Covered	T4,T5,T6
KmacIdle	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T5,T6,T16
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T6,T17,T19
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T5,T6,T16
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T5,T6,T16
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T5,T6,T16
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T6,T17,T19
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T4,T5,T6
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T4,T5,T6
KmacDigest	-	-	-	-	-	-	-	1	Covered	T4,T5,T6
KmacDigest	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	803	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1104	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1363	if ((!rst_ni))
-2-:	1365	if (alert_recov_operation)
-3-:	1367	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Not Covered
0	0	1	Covered	T20,T21,T22
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1386	if ((!rst_ni))
-2-:	1388	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T7,T8,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1415	if ((!rst_ni))
-2-:	1417	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T7,T8,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1425	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1322428	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	345170	0	0
EntrySizeRegSameToEntrySizePkg_A	1060	1060	0	0
ErrProcessedLatched_A	2147483647	548	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	80	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	80	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	80	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacFsmCheck_A	2147483647	80	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	80	0	0
FpvSecCmRoundCountCheck_A	2147483647	80	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	80	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	80	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	80	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1060	1060	0	0
NumEntriesRegSameToNumEntriesPkg_A	1060	1060	0	0
PrefixRegSameToPrefixPkg_A	1060	1060	0	0
SecretKeyDivideBy32_A	1060	1060	0	0
Sha3AbsorbedPulse_A	2147483647	355000	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1322428	0	0
T4	191736	1242	0	0
T5	528307	283	0	0
T6	311444	381	0	0
T7	3044	4	0	0
T13	177128	1205	0	0
T14	962806	781	0	0
T15	137468	997	0	0
T16	551569	949	0	0
T17	181884	96	0	0
T18	5846	31	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345170	0	0
T4	191736	380	0	0
T5	528307	63	0	0
T6	311444	84	0	0
T7	3044	1	0	0
T13	177128	358	0	0
T14	962806	242	0	0
T15	137468	301	0	0
T16	551569	125	0	0
T17	181884	22	0	0
T18	5846	9	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	548	0	0
T20	15021	3	0	0
T21	66490	15	0	0
T22	0	4	0	0
T23	0	19	0	0
T67	0	11	0	0
T68	0	16	0	0
T69	0	8	0	0
T70	0	14	0	0
T71	0	16	0	0
T72	0	5	0	0
T73	486426	0	0	0
T74	279908	0	0	0
T75	338210	0	0	0
T76	603244	0	0	0
T77	792925	0	0	0
T78	822545	0	0	0
T79	27920	0	0	0
T80	175545	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	355000	0	0
T4	191736	390	0	0
T5	528307	63	0	0
T6	311444	84	0	0
T7	3044	0	0	0
T13	177128	374	0	0
T14	962806	246	0	0
T15	137468	310	0	0
T16	551569	127	0	0
T17	181884	18	0	0
T18	5846	9	0	0
T19	0	80	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		163	157	96.32
ALWAYS	346	0	0
ALWAYS	346	2	2	100.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
ALWAYS	429	9	9	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
ALWAYS	488	6	6	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	539	0	0
CONT_ASSIGN	541	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
ALWAYS	563	5	5	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	582	1	1	100.00
CONT_ASSIGN	592	1	1	100.00
ALWAYS	612	3	3	100.00
CONT_ASSIGN	616	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	643	7	5	71.43
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	684	1	0	0.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
ALWAYS	721	3	3	100.00
ALWAYS	725	28	28	100.00
CONT_ASSIGN	875	1	1	100.00
CONT_ASSIGN	878	1	1	100.00
CONT_ASSIGN	942	1	1	100.00
CONT_ASSIGN	944	1	1	100.00
CONT_ASSIGN	974	1	1	100.00
CONT_ASSIGN	979	1	1	100.00
CONT_ASSIGN	980	1	1	100.00
CONT_ASSIGN	982	1	1	100.00
CONT_ASSIGN	985	0	0
ALWAYS	1103	0	0
ALWAYS	1103	2	2	100.00
CONT_ASSIGN	1255	1	0	0.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1257	1	1	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
CONT_ASSIGN	1357	1	1	100.00
ALWAYS	1363	6	5	83.33
CONT_ASSIGN	1372	1	1	100.00
CONT_ASSIGN	1374	1	1	100.00
ALWAYS	1386	4	4	100.00
CONT_ASSIGN	1392	1	1	100.00
ALWAYS	1415	4	4	100.00
ALWAYS	1425	3	3	100.00
CONT_ASSIGN	1436	1	1	100.00
CONT_ASSIGN	1440	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
346	1	1
347	1	1
352	0	1
421	1	1
422	1	1
426	1	1
429	1	1
430	1	1
431	1	1
432	1	1
434	1	1
436	1	1
440	1	1
444	1	1
448	1	1
464	1	1
465	1	1
466	1	1
469	1	1
473	1	1
474	1	1
478	1	1
481	1	1
488	1	1
489	1	1
490	1	1
491	1	1
492	1	1
493	1	1
			MISSING_ELSE
			MISSING_ELSE
513	1	1
518	1	1
525	1	1
528	1	1
529	1	1
530	1	1
533	5	5
534	5	5
537	1	1
539		unreachable
541	1	1
545	1	1
547	1	1
548	1	1
551	1	1
552	1	1
555	1	1
563	1	1
564	1	1
565	1	1
566	1	1
568	1	1
573	1	1
580	1	1
581	1	1
582	1	1
592	1	1
612	2	2
613	1	1
616	1	1
635	1	1
640	1	1
643	1	1
645	1	1
650	1	1
654	1	1
658	1	1
662	0	1
666	0	1
679	1	1
684	0	1
691	1	1
701	1	1
721	3	3
725	1	1
727	1	1
728	1	1
730	1	1
732	1	1
734	1	1
735	1	1
738	1	1
741	1	1
747	1	1
748	1	1
750	1	1
755	1	1
756	1	1
757	1	1
759	1	1
765	1	1
770	1	1
771	1	1
773	1	1
775	1	1
781	1	1
782	1	1
784	1	1
790	1	1
791	1	1
803	1	1
804	1	1
			MISSING_ELSE
875	1	1
878	1	1
942	1	1
944	1	1
974	1	1
979	1	1
980	1	1
982	1	1
985		unreachable
1103	1	1
1104	1	1
1255	0	1
1256	1	1
1257	1	1
1266	1	1
1272	1	1
1273	1	1
1274	1	1
1275	1	1
1278	1	1
1287	1	1
1331	1	1
1345	1	1
1352	1	1
1357	1	1
1363	1	1
1364	1	1
1365	1	1
1366	0	1
1367	1	1
1368	1	1
			MISSING_ELSE
1372	1	1
1374	1	1
1386	1	1
1387	1	1
1388	1	1
1389	1	1
			MISSING_ELSE
1392	1	1
1415	1	1
1416	1	1
1417	1	1
1419	1	1
			MISSING_ELSE
1425	1	1
1426	1	1
1429	1	1
1436	1	1
1440	1	1
1442	6	6

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	74	68	91.89
Logical	74	68	91.89
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T28,T26,T53

 LINE       541
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T28,T26,T53

 LINE       545
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T35,T37,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       552
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       565
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       565
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       565
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T4,T5,T6
1	-	Covered	T4,T5,T6

 LINE       573
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       616
 EXPRESSION (((~msgfifo_empty_q)) & msgfifo_empty)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       635
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T4,T5,T6
0	0	0	1	Covered	T45,T31,T54
0	0	1	0	Not Covered
0	1	0	0	Covered	T7,T8,T9
1	0	0	0	Covered	T25,T26,T27

 LINE       679
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T4,T5,T6
0	0	0	1	Not Covered
0	0	1	0	Covered	T10,T11,T12
0	1	0	0	Unreachable
1	0	0	0	Covered	T10,T11,T12

 LINE       691
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T4,T5,T6
0	0	0	0	0	1	Covered	T10,T11,T12
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T10,T11,T12
0	0	1	0	0	0	Covered	T10,T11,T12
0	1	0	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	0	Covered	T10,T11,T12

 LINE       732
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       734
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T16

 LINE       748
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T6,T17,T19
1	Covered	T5,T6,T16

 LINE       974
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       1104
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       1345
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T55,T56,T57
1	0	Covered	T4,T5,T6
1	1	Covered	T55,T56,T57

 LINE       1345
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T55,T56,T57
1	0	Covered	T4,T5,T6
1	1	Covered	T55,T56,T57

 LINE       1374
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T4,T5,T6
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T10,T11,T12
0	0	1	0	0	Covered	T7,T8,T9
0	1	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	64	64	100.00
Total Bits	4160	4160	100.00
Total Bits 0->1	2080	2080	100.00
Total Bits 1->0	2080	2080	100.00

Ports	64	64	100.00
Port Bits	4160	4160	100.00
Port Bits 0->1	2080	2080	100.00
Port Bits 1->0	2080	2080	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T58	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T2,T58	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T58	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T58	Yes	T2,T3,T58	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T58	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T58	Yes	T2,T3,T58	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T2,T3,T58	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T2,T58,T59	Yes	T2,T58,T59	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T2,T3,T58	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T58	Yes	T1,T2,T58	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T60	Yes	T1,T2,T60	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T58	Yes	T1,T2,T58	OUTPUT
keymgr_key_i.key[0][0]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][1]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][3:2]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][4]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][7:5]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][11:8]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][13:12]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][14]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][15]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][16]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][17]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][18]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][19]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][20]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][21]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][23:22]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][24]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][27:25]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][28]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][29]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][30]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][33:31]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][34]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][35]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][36]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][37]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][40:38]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][41]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][42]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][43]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][44]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][45]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][47:46]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][48]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][49]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][50]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][51]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][52]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][53]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][56:54]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][57]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][58]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][59]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][60]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][61]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][62]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][63]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][64]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][65]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][67:66]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][68]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][69]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][70]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][74:71]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][75]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][77:76]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][78]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][79]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][80]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][81]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][82]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][83]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][86:84]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][87]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][88]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][90:89]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][92:91]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][93]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][94]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][97:95]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][98]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][100:99]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][101]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][102]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][104:103]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][105]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][106]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][109:107]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][110]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][111]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][112]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][113]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][114]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][116:115]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][117]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][118]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][120:119]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][122:121]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][126:123]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][127]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][129:128]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][130]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][131]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][133:132]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][134]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][136:135]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][137]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][138]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][140:139]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][141]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][142]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][143]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][144]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][145]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][146]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][147]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][148]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][149]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][150]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][151]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][152]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][155:153]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][156]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][157]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][158]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][159]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][160]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][163:161]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][165:164]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][166]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][167]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][168]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][169]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][170]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][173:171]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][174]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][175]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][176]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][177]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][180:178]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][181]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][182]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][184:183]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][192:185]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][193]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][195:194]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][196]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][197]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][198]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][199]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][200]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][208:201]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][209]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][210]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][212:211]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][213]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][214]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][215]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][216]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][217]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][218]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][219]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][220]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][221]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][222]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][223]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][224]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][226:225]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][227]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][228]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][229]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][230]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][231]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][232]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][233]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][234]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][235]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][236]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][237]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][239:238]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][240]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][241]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][243:242]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][244]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][246:245]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][248:247]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][250:249]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][251]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][252]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][253]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][254]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[0][255]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][4:0]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][5]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][6]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][7]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][8]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][9]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][10]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][11]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][18:12]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][19]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][20]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][21]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][23:22]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][24]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][25]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][26]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][27]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][28]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][29]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][33:30]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][34]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][36:35]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][37]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][38]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][39]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][42:40]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][43]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][44]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][47:45]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][48]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][49]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][51:50]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][52]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][54:53]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][56:55]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][57]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][58]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][61:59]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][62]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][63]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][66:64]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][68:67]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][69]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][71:70]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][75:72]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][76]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][77]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][79:78]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][81:80]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][82]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][83]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][84]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][85]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][86]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][89:87]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][90]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][91]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][92]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][93]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][94]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][95]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][96]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][97]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][100:98]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][101]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][102]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][104:103]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][105]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][107:106]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][108]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][109]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][110]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][112:111]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][113]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][114]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][115]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][117:116]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][118]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][119]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][120]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][122:121]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][123]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][125:124]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][126]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][128:127]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][129]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][131:130]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][134:132]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][135]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][136]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][137]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][138]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][139]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][140]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][141]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][142]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][143]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][147:144]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][149:148]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][150]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][151]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][152]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][153]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][156:154]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][159:157]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][160]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][161]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][162]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][163]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][168:164]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][169]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][170]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][172:171]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][173]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][174]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][175]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][177:176]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][178]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][179]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][181:180]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][184:182]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][185]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][186]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][188:187]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][190:189]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][193:191]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][194]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][197:195]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][200:198]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][202:201]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][203]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][204]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][205]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][206]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][207]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][208]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][210:209]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][211]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][212]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][213]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][214]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][215]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][216]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][217]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][219:218]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][221:220]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][222]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][223]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][224]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][225]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][226]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][229:227]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][230]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][231]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][232]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][233]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][234]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][237:235]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][238]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][241:239]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][242]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][244:243]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][245]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][246]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][247]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][248]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][249]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][252:250]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][253]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.key[1][255:254]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
keymgr_key_i.valid	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
app_i[0].last	Yes	Yes	T6,T19,T30	Yes	T6,T17,T19	INPUT
app_i[0].strb[7:0]	Yes	Yes	T6,T17,T30	Yes	T6,T17,T30	INPUT
app_i[0].data[63:0]	Yes	Yes	T6,T17,T19	Yes	T6,T17,T19	INPUT
app_i[0].valid	Yes	Yes	T6,T7,T17	Yes	T6,T7,T17	INPUT
app_i[1].last	Yes	Yes	T6,T19,T30	Yes	T6,T19,T30	INPUT
app_i[1].strb[7:0]	Yes	Yes	T6,T17,T30	Yes	T6,T17,T30	INPUT
app_i[1].data[63:0]	Yes	Yes	T6,T17,T19	Yes	T6,T17,T19	INPUT
app_i[1].valid	Yes	Yes	T6,T7,T17	Yes	T6,T7,T17	INPUT
app_i[2].last	Yes	Yes	T6,T19,T25	Yes	T6,T19,T29	INPUT
app_i[2].strb[7:0]	Yes	Yes	T6,T30,T36	Yes	T6,T30,T36	INPUT
app_i[2].data[63:0]	Yes	Yes	T6,T19,T29	Yes	T6,T19,T29	INPUT
app_i[2].valid	Yes	Yes	T6,T7,T19	Yes	T6,T7,T19	INPUT
app_o[0].error	Yes	Yes	T2,T60,T61	Yes	T2,T60,T61	OUTPUT
app_o[0].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[0].digest_share0[383:0]	Yes	Yes	T6,T19,T30	Yes	T6,T19,T30	OUTPUT
app_o[0].done	Yes	Yes	T6,T17,T19	Yes	T6,T17,T19	OUTPUT
app_o[0].ready	Yes	Yes	T6,T17,T19	Yes	T6,T17,T19	OUTPUT
app_o[1].error	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
app_o[1].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[1].digest_share0[383:0]	Yes	Yes	T6,T19,T30	Yes	T6,T19,T30	OUTPUT
app_o[1].done	Yes	Yes	T6,T19,T30	Yes	T6,T19,T30	OUTPUT
app_o[1].ready	Yes	Yes	T6,T17,T19	Yes	T6,T17,T19	OUTPUT
app_o[2].error	Yes	Yes	T25,T27,T39	Yes	T25,T27,T39	OUTPUT
app_o[2].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[2].digest_share0[383:0]	Yes	Yes	T6,T29,T30	Yes	T6,T29,T30	OUTPUT
app_o[2].done	Yes	Yes	T6,T19,T29	Yes	T6,T19,T29	OUTPUT
app_o[2].ready	Yes	Yes	T6,T19,T29	Yes	T6,T19,T29	OUTPUT
entropy_o.edn_req[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_bus[31:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_fips[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_ack[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
lc_escalate_en_i[3:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
intr_kmac_done_o	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
intr_fifo_empty_o	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
intr_kmac_err_o	Yes	Yes	T2,T63,T66	Yes	T2,T63,T66	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T2,T60,T61	Yes	T2,T60,T61	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	773	Covered	T1
KmacIdle	741	Covered	T1
KmacKeyBlock	748	Covered	T1
KmacMsgFeed	738	Covered	T1
KmacPrefix	735	Covered	T1
KmacTerminalError	790	Covered	T1

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	782	Covered	T1
KmacDigest->KmacTerminalError	804	Covered	T1
KmacIdle->KmacMsgFeed	738	Covered	T1
KmacIdle->KmacPrefix	735	Covered	T1
KmacIdle->KmacTerminalError	804	Covered	T1
KmacKeyBlock->KmacMsgFeed	757	Covered	T1
KmacKeyBlock->KmacTerminalError	804	Covered	T1
KmacMsgFeed->KmacDigest	773	Covered	T1
KmacMsgFeed->KmacIdle	770	Covered	T1
KmacMsgFeed->KmacTerminalError	804	Covered	T1
KmacPrefix->KmacKeyBlock	748	Covered	T1
KmacPrefix->KmacMsgFeed	748	Covered	T1
KmacPrefix->KmacTerminalError	804	Covered	T1

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		55	51	92.73
TERNARY	426	2	2	100.00
CASE	434	6	5	83.33
IF	488	3	3	100.00
IF	563	3	3	100.00
IF	612	2	2	100.00
CASE	645	6	4	66.67
IF	721	2	2	100.00
CASE	730	15	15	100.00
IF	803	2	2	100.00
TERNARY	1104	2	2	100.00
IF	1363	4	3	75.00
IF	1386	3	3	100.00
IF	1415	3	3	100.00
IF	1425	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	426	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	434	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T4,T5,T6
CmdProcess	Covered	T4,T5,T6
CmdManualRun	Covered	T5,T6,T16
CmdDone	Covered	T4,T5,T6
CmdNone	Covered	T4,T5,T6
default	Not Covered

	LineNo.	Expression
-1-:	488	if ((!rst_ni))
-2-:	490	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	563	if ((!rst_ni))
-2-:	565	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	612	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	645	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T7,T8,T9
errchecker_err.valid	Covered	T45,T31,T54
sha3_err.valid	Covered	T25,T26,T27
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	721	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	730	case (kmac_st)
-2-:	732	if ((kmac_cmd == CmdStart))
-3-:	734	if ((CShake == app_sha3_mode))
-4-:	747	if (sha3_block_processed)
-5-:	748	(app_kmac_en) ? 
-6-:	756	if (sha3_block_processed)
-7-:	765	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	771	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	781	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T5,T6,T16
KmacIdle	1	0	-	-	-	-	-	-	Covered	T4,T5,T6
KmacIdle	0	-	-	-	-	-	-	-	Covered	T4,T5,T6
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T5,T6,T16
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T6,T17,T19
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T5,T6,T16
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T5,T6,T16
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T5,T6,T16
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T6,T17,T19
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T4,T5,T6
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T4,T5,T6
KmacDigest	-	-	-	-	-	-	-	1	Covered	T4,T5,T6
KmacDigest	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	803	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1104	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1363	if ((!rst_ni))
-2-:	1365	if (alert_recov_operation)
-3-:	1367	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Not Covered
0	0	1	Covered	T20,T21,T22
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1386	if ((!rst_ni))
-2-:	1388	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T7,T8,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1415	if ((!rst_ni))
-2-:	1417	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T7,T8,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	1425	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1322428	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	345170	0	0
EntrySizeRegSameToEntrySizePkg_A	1060	1060	0	0
ErrProcessedLatched_A	2147483647	548	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	80	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	80	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	80	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacFsmCheck_A	2147483647	80	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	80	0	0
FpvSecCmRoundCountCheck_A	2147483647	80	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	80	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	80	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	80	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1060	1060	0	0
NumEntriesRegSameToNumEntriesPkg_A	1060	1060	0	0
PrefixRegSameToPrefixPkg_A	1060	1060	0	0
SecretKeyDivideBy32_A	1060	1060	0	0
Sha3AbsorbedPulse_A	2147483647	355000	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1322428	0	0
T4	191736	1242	0	0
T5	528307	283	0	0
T6	311444	381	0	0
T7	3044	4	0	0
T13	177128	1205	0	0
T14	962806	781	0	0
T15	137468	997	0	0
T16	551569	949	0	0
T17	181884	96	0	0
T18	5846	31	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345170	0	0
T4	191736	380	0	0
T5	528307	63	0	0
T6	311444	84	0	0
T7	3044	1	0	0
T13	177128	358	0	0
T14	962806	242	0	0
T15	137468	301	0	0
T16	551569	125	0	0
T17	181884	22	0	0
T18	5846	9	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	548	0	0
T20	15021	3	0	0
T21	66490	15	0	0
T22	0	4	0	0
T23	0	19	0	0
T67	0	11	0	0
T68	0	16	0	0
T69	0	8	0	0
T70	0	14	0	0
T71	0	16	0	0
T72	0	5	0	0
T73	486426	0	0	0
T74	279908	0	0	0
T75	338210	0	0	0
T76	603244	0	0	0
T77	792925	0	0	0
T78	822545	0	0	0
T79	27920	0	0	0
T80	175545	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	601848	20	0	0
T11	0	10	0	0
T12	0	20	0	0
T33	187006	0	0	0
T70	72837	0	0	0
T81	0	20	0	0
T82	0	10	0	0
T83	424533	0	0	0
T84	211090	0	0	0
T85	361787	0	0	0
T86	250447	0	0	0
T87	52505	0	0	0
T88	136263	0	0	0
T89	143357	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	355000	0	0
T4	191736	390	0	0
T5	528307	63	0	0
T6	311444	84	0	0
T7	3044	0	0	0
T13	177128	374	0	0
T14	962806	246	0	0
T15	137468	310	0	0
T16	551569	127	0	0
T17	181884	18	0	0
T18	5846	9	0	0
T19	0	80	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0