Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	96.32	91.89	100.00	100.00	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1784654	0	0
entropy_period_rd_A	2147483647	2900	0	0
intr_enable_rd_A	2147483647	3492	0	0
prefix_0_rd_A	2147483647	2762	0	0
prefix_10_rd_A	2147483647	2863	0	0
prefix_1_rd_A	2147483647	2854	0	0
prefix_2_rd_A	2147483647	2815	0	0
prefix_3_rd_A	2147483647	2900	0	0
prefix_4_rd_A	2147483647	2817	0	0
prefix_5_rd_A	2147483647	2830	0	0
prefix_6_rd_A	2147483647	2645	0	0
prefix_7_rd_A	2147483647	2861	0	0
prefix_8_rd_A	2147483647	2857	0	0
prefix_9_rd_A	2147483647	3007	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1784654	0	0
T2	5367	1	0	0
T3	3960	0	0	0
T58	1698	0	0	0
T59	4139	116	0	0
T60	3704	0	0	0
T61	1529	0	0	0
T62	1488	0	0	0
T63	1361	0	0	0
T66	0	2	0	0
T90	6627	0	0	0
T91	918	0	0	0
T92	0	18	0	0
T93	0	192	0	0
T94	0	130	0	0
T95	0	166	0	0
T100	0	1	0	0
T122	0	2	0	0
T124	0	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2900	0	0
T64	1707	0	0	0
T65	1075	0	0	0
T92	2153	0	0	0
T93	3766	0	0	0
T96	0	7	0	0
T99	155020	223	0	0
T105	2609	5	0	0
T114	0	17	0	0
T122	12430	86	0	0
T124	0	59	0	0
T125	0	13	0	0
T128	5888	3	0	0
T130	0	58	0	0
T136	10150	0	0	0
T137	866	0	0	0
T138	0	127	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3492	0	0
T60	3704	0	0	0
T61	1529	0	0	0
T62	1488	6	0	0
T63	1361	9	0	0
T64	1707	23	0	0
T66	32525	0	0	0
T90	6627	5	0	0
T91	918	0	0	0
T92	2153	0	0	0
T99	155020	480	0	0
T105	0	2	0	0
T122	0	86	0	0
T125	0	13	0	0
T128	0	5	0	0
T139	0	13	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2762	0	0
T63	1361	0	0	0
T64	1707	0	0	0
T66	32525	0	0	0
T90	6627	1	0	0
T91	918	0	0	0
T92	2153	0	0	0
T93	3766	0	0	0
T94	0	2	0	0
T96	0	2	0	0
T99	155020	400	0	0
T105	2609	0	0	0
T114	0	8	0	0
T122	12430	34	0	0
T124	0	67	0	0
T128	0	29	0	0
T130	0	49	0	0
T138	0	184	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2863	0	0
T63	1361	0	0	0
T64	1707	0	0	0
T66	32525	0	0	0
T90	6627	14	0	0
T91	918	0	0	0
T92	2153	0	0	0
T93	3766	0	0	0
T96	0	9	0	0
T99	155020	467	0	0
T105	2609	6	0	0
T114	0	4	0	0
T122	12430	58	0	0
T124	0	24	0	0
T128	0	17	0	0
T130	0	44	0	0
T138	0	233	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2854	0	0
T63	1361	0	0	0
T64	1707	0	0	0
T66	32525	0	0	0
T90	6627	10	0	0
T91	918	0	0	0
T92	2153	0	0	0
T93	3766	0	0	0
T94	0	5	0	0
T96	0	1	0	0
T99	155020	487	0	0
T105	2609	11	0	0
T122	12430	54	0	0
T124	0	65	0	0
T125	0	11	0	0
T128	0	7	0	0
T130	0	13	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2815	0	0
T63	1361	0	0	0
T64	1707	0	0	0
T66	32525	0	0	0
T90	6627	15	0	0
T91	918	0	0	0
T92	2153	0	0	0
T93	3766	0	0	0
T96	0	7	0	0
T99	155020	461	0	0
T105	2609	4	0	0
T114	0	19	0	0
T122	12430	44	0	0
T124	0	68	0	0
T125	0	13	0	0
T128	0	9	0	0
T130	0	28	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2900	0	0
T63	1361	0	0	0
T64	1707	0	0	0
T66	32525	0	0	0
T90	6627	8	0	0
T91	918	0	0	0
T92	2153	0	0	0
T93	3766	0	0	0
T96	0	1	0	0
T99	155020	445	0	0
T105	2609	8	0	0
T114	0	13	0	0
T122	12430	37	0	0
T124	0	48	0	0
T125	0	3	0	0
T128	0	19	0	0
T130	0	9	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2817	0	0
T63	1361	0	0	0
T64	1707	0	0	0
T66	32525	0	0	0
T90	6627	20	0	0
T91	918	0	0	0
T92	2153	0	0	0
T93	3766	0	0	0
T96	0	8	0	0
T99	155020	474	0	0
T105	2609	4	0	0
T114	0	19	0	0
T122	12430	42	0	0
T124	0	52	0	0
T125	0	2	0	0
T128	0	8	0	0
T130	0	22	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2830	0	0
T63	1361	0	0	0
T64	1707	0	0	0
T66	32525	0	0	0
T90	6627	3	0	0
T91	918	0	0	0
T92	2153	0	0	0
T93	3766	0	0	0
T99	155020	420	0	0
T105	2609	2	0	0
T114	0	5	0	0
T122	12430	55	0	0
T124	0	35	0	0
T125	0	3	0	0
T128	0	7	0	0
T130	0	40	0	0
T138	0	222	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2645	0	0
T63	1361	0	0	0
T64	1707	0	0	0
T66	32525	0	0	0
T90	6627	25	0	0
T91	918	0	0	0
T92	2153	0	0	0
T93	3766	0	0	0
T96	0	7	0	0
T99	155020	422	0	0
T105	2609	0	0	0
T114	0	5	0	0
T122	12430	43	0	0
T124	0	51	0	0
T125	0	5	0	0
T128	0	9	0	0
T130	0	28	0	0
T138	0	202	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2861	0	0
T63	1361	0	0	0
T64	1707	0	0	0
T66	32525	0	0	0
T90	6627	14	0	0
T91	918	0	0	0
T92	2153	0	0	0
T93	3766	0	0	0
T96	0	1	0	0
T99	155020	448	0	0
T105	2609	0	0	0
T114	0	6	0	0
T122	12430	42	0	0
T124	0	38	0	0
T125	0	12	0	0
T130	0	33	0	0
T138	0	191	0	0
T140	0	13	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2857	0	0
T63	1361	0	0	0
T64	1707	0	0	0
T66	32525	0	0	0
T90	6627	15	0	0
T91	918	0	0	0
T92	2153	0	0	0
T93	3766	0	0	0
T96	0	9	0	0
T99	155020	514	0	0
T105	2609	0	0	0
T114	0	17	0	0
T122	12430	51	0	0
T124	0	57	0	0
T125	0	1	0	0
T128	0	3	0	0
T130	0	60	0	0
T138	0	232	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3007	0	0
T63	1361	0	0	0
T64	1707	0	0	0
T66	32525	0	0	0
T90	6627	6	0	0
T91	918	0	0	0
T92	2153	0	0	0
T93	3766	0	0	0
T96	0	3	0	0
T99	155020	494	0	0
T105	2609	10	0	0
T114	0	11	0	0
T122	12430	24	0	0
T124	0	52	0	0
T128	0	5	0	0
T130	0	51	0	0
T138	0	210	0	0