Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57518	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

121947

1

T1

191

T2

99

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	108810	1			T1	120		T2	79		T3	11
values[0x0]	33781	1			T1	60		T2	30		T3	7
values[0x1]	36874	1			T1	60		T2	30		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42305	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

137160

1

T1

203

T2

112

T3

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	779	1			T4	14		T11	2		T5	6
valid_sources[0x01]	781	1			T4	9		T11	1		T5	12
valid_sources[0x02]	517	1			T4	12		T5	17		T6	2
valid_sources[0x03]	655	1			T4	12		T11	3		T5	8
valid_sources[0x04]	582	1			T4	2		T11	2		T5	16
valid_sources[0x05]	808	1			T4	4		T5	13		T10	1
valid_sources[0x06]	723	1			T4	23		T11	1		T5	18
valid_sources[0x07]	721	1			T4	11		T5	9		T14	1
valid_sources[0x08]	508	1			T2	1		T4	12		T11	3
valid_sources[0x09]	615	1			T4	7		T5	12		T12	1
valid_sources[0x0a]	593	1			T2	4		T4	24		T5	12
valid_sources[0x0b]	646	1			T4	4		T5	9		T6	2
valid_sources[0x0c]	726	1			T4	15		T11	1		T5	8
valid_sources[0x0d]	539	1			T4	13		T5	15		T6	1
valid_sources[0x0e]	732	1			T4	6		T5	10		T9	1
valid_sources[0x0f]	666	1			T4	5		T11	1		T5	7
valid_sources[0x10]	804	1			T4	5		T5	8		T6	1
valid_sources[0x11]	641	1			T4	14		T5	12		T6	2
valid_sources[0x12]	821	1			T4	11		T11	1		T5	14
valid_sources[0x13]	492	1			T2	1		T4	19		T5	8
valid_sources[0x14]	681	1			T4	16		T5	7		T10	1
valid_sources[0x15]	684	1			T4	3		T11	5		T5	13
valid_sources[0x16]	574	1			T2	1		T4	5		T11	2
valid_sources[0x17]	525	1			T4	5		T11	1		T5	13
valid_sources[0x18]	819	1			T4	14		T11	1		T5	12
valid_sources[0x19]	661	1			T2	2		T4	3		T5	8
valid_sources[0x1a]	675	1			T4	13		T11	2		T5	11
valid_sources[0x1b]	681	1			T2	1		T4	3		T11	2
valid_sources[0x1c]	738	1			T4	6		T11	3		T5	13
valid_sources[0x1d]	606	1			T2	1		T4	5		T11	8
valid_sources[0x1e]	560	1			T4	26		T11	1		T5	12
valid_sources[0x1f]	706	1			T2	1		T4	11		T5	14
valid_sources[0x20]	726	1			T4	14		T5	12		T12	4
valid_sources[0x21]	738	1			T4	15		T5	7		T12	1
valid_sources[0x22]	689	1			T2	1		T4	8		T11	7
valid_sources[0x23]	656	1			T4	10		T11	1		T5	14
valid_sources[0x24]	882	1			T4	8		T11	3		T5	7
valid_sources[0x25]	865	1			T1	6		T4	12		T11	1
valid_sources[0x26]	583	1			T4	7		T5	14		T10	1
valid_sources[0x27]	865	1			T4	14		T5	15		T12	3
valid_sources[0x28]	851	1			T4	9		T11	1		T5	17
valid_sources[0x29]	654	1			T2	1		T4	9		T11	2
valid_sources[0x2a]	693	1			T2	1		T4	4		T5	12
valid_sources[0x2b]	926	1			T4	12		T5	9		T6	1
valid_sources[0x2c]	771	1			T4	14		T11	8		T5	16
valid_sources[0x2d]	601	1			T2	1		T4	9		T11	1
valid_sources[0x2e]	738	1			T2	3		T4	14		T5	12
valid_sources[0x2f]	594	1			T4	6		T11	3		T5	7
valid_sources[0x30]	743	1			T1	28		T4	20		T11	4
valid_sources[0x31]	909	1			T4	14		T5	12		T9	1
valid_sources[0x32]	655	1			T4	6		T5	13		T13	2
valid_sources[0x33]	817	1			T2	1		T4	5		T5	18
valid_sources[0x34]	822	1			T4	7		T5	7		T12	1
valid_sources[0x35]	542	1			T4	13		T5	16		T6	1
valid_sources[0x36]	893	1			T2	1		T4	6		T5	13
valid_sources[0x37]	706	1			T4	8		T11	1		T5	10
valid_sources[0x38]	627	1			T2	1		T4	21		T5	13
valid_sources[0x39]	720	1			T4	20		T5	9		T6	1
valid_sources[0x3a]	720	1			T4	5		T5	10		T6	1
valid_sources[0x3b]	608	1			T4	6		T5	14		T6	1
valid_sources[0x3c]	827	1			T4	6		T5	18		T6	1
valid_sources[0x3d]	632	1			T1	1		T4	19		T5	11
valid_sources[0x3e]	565	1			T4	14		T11	1		T5	12
valid_sources[0x3f]	577	1			T4	16		T5	11		T12	2
valid_sources[0x40]	741	1			T2	1		T4	15		T5	5
valid_sources[0x41]	770	1			T3	22		T4	10		T11	1
valid_sources[0x42]	558	1			T2	3		T4	5		T5	14
valid_sources[0x43]	739	1			T4	11		T5	12		T10	1
valid_sources[0x44]	822	1			T4	8		T11	3		T5	12
valid_sources[0x45]	622	1			T2	1		T4	14		T5	14
valid_sources[0x46]	681	1			T2	1		T4	12		T5	13
valid_sources[0x47]	1010	1			T2	1		T4	16		T5	8
valid_sources[0x48]	592	1			T2	2		T4	5		T5	10
valid_sources[0x49]	578	1			T2	2		T4	13		T5	3
valid_sources[0x4a]	761	1			T4	8		T5	12		T10	1
valid_sources[0x4b]	601	1			T4	6		T11	2		T5	8
valid_sources[0x4c]	908	1			T1	4		T2	1		T4	23
valid_sources[0x4d]	640	1			T4	20		T11	1		T5	11
valid_sources[0x4e]	650	1			T2	1		T4	7		T5	6
valid_sources[0x4f]	690	1			T1	6		T2	1		T4	11
valid_sources[0x50]	677	1			T2	4		T4	13		T5	13
valid_sources[0x51]	633	1			T2	3		T4	7		T5	10
valid_sources[0x52]	681	1			T4	5		T11	1		T5	12
valid_sources[0x53]	688	1			T4	15		T5	7		T6	1
valid_sources[0x54]	731	1			T4	4		T5	7		T12	2
valid_sources[0x55]	686	1			T4	7		T11	1		T5	10
valid_sources[0x56]	695	1			T4	10		T11	1		T5	14
valid_sources[0x57]	763	1			T4	5		T5	11		T12	4
valid_sources[0x58]	662	1			T4	25		T11	3		T5	11
valid_sources[0x59]	669	1			T2	2		T4	7		T11	3
valid_sources[0x5a]	592	1			T4	16		T8	40		T11	2
valid_sources[0x5b]	970	1			T4	4		T5	9		T12	1
valid_sources[0x5c]	738	1			T2	1		T4	11		T5	12
valid_sources[0x5d]	691	1			T4	4		T5	12		T12	1
valid_sources[0x5e]	757	1			T2	4		T4	9		T5	8
valid_sources[0x5f]	571	1			T4	11		T11	3		T5	7
valid_sources[0x60]	581	1			T2	3		T4	14		T5	11
valid_sources[0x61]	679	1			T4	5		T5	12		T10	1
valid_sources[0x62]	800	1			T4	9		T11	3		T5	7
valid_sources[0x63]	579	1			T1	32		T4	9		T11	1
valid_sources[0x64]	594	1			T2	1		T4	4		T11	3
valid_sources[0x65]	751	1			T2	3		T4	5		T5	6
valid_sources[0x66]	694	1			T4	11		T5	15		T6	2
valid_sources[0x67]	705	1			T4	12		T11	1		T5	8
valid_sources[0x68]	981	1			T4	22		T11	1		T5	16
valid_sources[0x69]	913	1			T2	2		T5	10		T12	1
valid_sources[0x6a]	816	1			T1	14		T4	6		T11	1
valid_sources[0x6b]	836	1			T1	28		T4	17		T11	1
valid_sources[0x6c]	644	1			T4	7		T11	2		T5	8
valid_sources[0x6d]	812	1			T2	1		T4	8		T5	8
valid_sources[0x6e]	765	1			T1	49		T4	8		T11	1
valid_sources[0x6f]	763	1			T4	18		T5	11		T12	2
valid_sources[0x70]	816	1			T1	4		T4	4		T5	6
valid_sources[0x71]	900	1			T4	12		T11	1		T5	10
valid_sources[0x72]	590	1			T2	3		T4	19		T5	12
valid_sources[0x73]	507	1			T2	1		T4	5		T11	2
valid_sources[0x74]	633	1			T2	1		T4	4		T5	10
valid_sources[0x75]	560	1			T4	8		T5	9		T12	11
valid_sources[0x76]	509	1			T4	15		T5	7		T12	1
valid_sources[0x77]	650	1			T4	3		T5	6		T12	1
valid_sources[0x78]	653	1			T4	4		T5	12		T12	1
valid_sources[0x79]	597	1			T4	10		T11	2		T5	8
valid_sources[0x7a]	722	1			T4	7		T5	12		T6	3
valid_sources[0x7b]	1084	1			T4	5		T5	10		T6	1
valid_sources[0x7c]	889	1			T4	7		T11	1		T5	8
valid_sources[0x7d]	559	1			T2	3		T4	17		T11	3
valid_sources[0x7e]	636	1			T2	1		T4	8		T5	13
valid_sources[0x7f]	540	1			T4	20		T5	7		T6	1
valid_sources[0x80]	584	1			T4	9		T5	10		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61393

1

T1

79

T2

43

T3

7

values[0x0]

all_enables

biggest_size

30483

1

T1

58

T2

29

T3

2

values[0x1]

all_enables

biggest_size

30071

1

T1

54

T2

27

T3

2