Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

71655

1

T1

49

T2

40

T3

11

full_word

122781

1

T1

191

T2

99

T3

11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	194096	1			T1	240		T2	139		T3	22
auto[TlIntgErrCmd]	106	1			T4	7		T5	3		T26	2
auto[TlIntgErrData]	120	1			T4	9		T5	10		T26	4
auto[TlIntgErrBoth]	114	1			T4	4		T5	7		T26	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111471

1

T1

120

T2

79

T3

11

auto[1]

82965

1

T1

120

T2

60

T3

11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	49706	1			T1	41		T2	36		T3	4
auto[TlIntgErrNone]	partial	auto[1]	21637	1			T1	8		T2	4		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	61618	1			T1	79		T2	43		T3	7
auto[TlIntgErrNone]	full_word	auto[1]	61135	1			T1	112		T2	56		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T4	1		T26	1		T28	3
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T4	5		T5	3		T26	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T72	1		T74	2		T75	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T4	1		T76	1		T73	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T4	6		T5	2		T26	1
auto[TlIntgErrData]	partial	auto[1]	57	1			T4	3		T5	8		T26	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T77	1		T75	1		T78	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T73	1		T75	1		T79	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T4	2		T5	5		T26	1
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T4	2		T5	2		T26	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T28	1		T80	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T80	1		T79	2		T81	1