Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1399749	16116	0	0
DepthKnown_A	1399749	1345295	0	0
RvalidKnown_A	1399749	1345295	0	0
WreadyKnown_A	1399749	1345295	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	16116	0	0
T5	25804	0	0	0
T6	1121	143	0	0
T9	1675	0	0	0
T10	1113	0	0	0
T11	2378	275	0	0
T12	4475	868	0	0
T13	2086	120	0	0
T14	0	265	0	0
T15	0	471	0	0
T16	0	233	0	0
T17	0	68	0	0
T18	0	670	0	0
T19	0	195	0	0
T23	1053	0	0	0
T24	3647	0	0	0
T25	1445	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	1345295	0	0
T1	3286	3217	0	0
T2	2229	2138	0	0
T3	1019	935	0	0
T4	13598	11994	0	0
T5	25804	24166	0	0
T6	1121	1020	0	0
T7	964	877	0	0
T8	1872	1819	0	0
T10	1113	1052	0	0
T11	2378	2322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	1345295	0	0
T1	3286	3217	0	0
T2	2229	2138	0	0
T3	1019	935	0	0
T4	13598	11994	0	0
T5	25804	24166	0	0
T6	1121	1020	0	0
T7	964	877	0	0
T8	1872	1819	0	0
T10	1113	1052	0	0
T11	2378	2322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	1345295	0	0
T1	3286	3217	0	0
T2	2229	2138	0	0
T3	1019	935	0	0
T4	13598	11994	0	0
T5	25804	24166	0	0
T6	1121	1020	0	0
T7	964	877	0	0
T8	1872	1819	0	0
T10	1113	1052	0	0
T11	2378	2322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1399749	19300	0	0
DepthKnown_A	1399749	1345295	0	0
RvalidKnown_A	1399749	1345295	0	0
WreadyKnown_A	1399749	1345295	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	19300	0	0
T5	25804	0	0	0
T6	1121	82	0	0
T9	1675	0	0	0
T10	1113	0	0	0
T11	2378	256	0	0
T12	4475	1887	0	0
T13	2086	114	0	0
T14	0	218	0	0
T15	0	379	0	0
T16	0	777	0	0
T17	0	68	0	0
T18	0	1555	0	0
T19	0	159	0	0
T23	1053	0	0	0
T24	3647	0	0	0
T25	1445	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	1345295	0	0
T1	3286	3217	0	0
T2	2229	2138	0	0
T3	1019	935	0	0
T4	13598	11994	0	0
T5	25804	24166	0	0
T6	1121	1020	0	0
T7	964	877	0	0
T8	1872	1819	0	0
T10	1113	1052	0	0
T11	2378	2322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	1345295	0	0
T1	3286	3217	0	0
T2	2229	2138	0	0
T3	1019	935	0	0
T4	13598	11994	0	0
T5	25804	24166	0	0
T6	1121	1020	0	0
T7	964	877	0	0
T8	1872	1819	0	0
T10	1113	1052	0	0
T11	2378	2322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	1345295	0	0
T1	3286	3217	0	0
T2	2229	2138	0	0
T3	1019	935	0	0
T4	13598	11994	0	0
T5	25804	24166	0	0
T6	1121	1020	0	0
T7	964	877	0	0
T8	1872	1819	0	0
T10	1113	1052	0	0
T11	2378	2322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1399749	290411	0	0
DepthKnown_A	1399749	1345295	0	0
RvalidKnown_A	1399749	1345295	0	0
WreadyKnown_A	1399749	1345295	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	290411	0	0
T1	3286	648	0	0
T2	2229	316	0	0
T3	1019	22	0	0
T4	13598	5244	0	0
T5	25804	6024	0	0
T6	1121	265	0	0
T7	964	22	0	0
T8	1872	40	0	0
T10	1113	40	0	0
T11	2378	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	1345295	0	0
T1	3286	3217	0	0
T2	2229	2138	0	0
T3	1019	935	0	0
T4	13598	11994	0	0
T5	25804	24166	0	0
T6	1121	1020	0	0
T7	964	877	0	0
T8	1872	1819	0	0
T10	1113	1052	0	0
T11	2378	2322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	1345295	0	0
T1	3286	3217	0	0
T2	2229	2138	0	0
T3	1019	935	0	0
T4	13598	11994	0	0
T5	25804	24166	0	0
T6	1121	1020	0	0
T7	964	877	0	0
T8	1872	1819	0	0
T10	1113	1052	0	0
T11	2378	2322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	1345295	0	0
T1	3286	3217	0	0
T2	2229	2138	0	0
T3	1019	935	0	0
T4	13598	11994	0	0
T5	25804	24166	0	0
T6	1121	1020	0	0
T7	964	877	0	0
T8	1872	1819	0	0
T10	1113	1052	0	0
T11	2378	2322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1399749	410682	0	0
DepthKnown_A	1399749	1345295	0	0
RvalidKnown_A	1399749	1345295	0	0
WreadyKnown_A	1399749	1345295	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	410682	0	0
T1	3286	1190	0	0
T2	2229	661	0	0
T3	1019	22	0	0
T4	13598	2682	0	0
T5	25804	12808	0	0
T6	1121	146	0	0
T7	964	22	0	0
T8	1872	113	0	0
T10	1113	124	0	0
T11	2378	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	1345295	0	0
T1	3286	3217	0	0
T2	2229	2138	0	0
T3	1019	935	0	0
T4	13598	11994	0	0
T5	25804	24166	0	0
T6	1121	1020	0	0
T7	964	877	0	0
T8	1872	1819	0	0
T10	1113	1052	0	0
T11	2378	2322	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	1345295	0	0
T1	3286	3217	0	0
T2	2229	2138	0	0
T3	1019	935	0	0
T4	13598	11994	0	0
T5	25804	24166	0	0
T6	1121	1020	0	0
T7	964	877	0	0
T8	1872	1819	0	0
T10	1113	1052	0	0
T11	2378	2322	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	1345295	0	0
T1	3286	3217	0	0
T2	2229	2138	0	0
T3	1019	935	0	0
T4	13598	11994	0	0
T5	25804	24166	0	0
T6	1121	1020	0	0
T7	964	877	0	0
T8	1872	1819	0	0
T10	1113	1052	0	0
T11	2378	2322	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0