Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
1.74	0.00	0.00	8.70	0.00	0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1399749	3065	0	0
entropy_period_rd_A	1399749	2259	0	0
intr_enable_rd_A	1399749	3203	0	0
prefix_0_rd_A	1399749	2260	0	0
prefix_10_rd_A	1399749	2419	0	0
prefix_1_rd_A	1399749	2100	0	0
prefix_2_rd_A	1399749	2122	0	0
prefix_3_rd_A	1399749	2310	0	0
prefix_4_rd_A	1399749	2185	0	0
prefix_5_rd_A	1399749	2225	0	0
prefix_6_rd_A	1399749	2022	0	0
prefix_7_rd_A	1399749	2243	0	0
prefix_8_rd_A	1399749	2322	0	0
prefix_9_rd_A	1399749	2173	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	3065	0	0
T4	13598	1	0	0
T5	25804	0	0	0
T6	1121	1	0	0
T7	964	0	0	0
T8	1872	0	0	0
T9	1675	0	0	0
T10	1113	0	0	0
T11	2378	0	0	0
T12	4475	0	0	0
T14	0	139	0	0
T15	0	161	0	0
T16	0	25	0	0
T17	0	110	0	0
T18	0	254	0	0
T19	0	116	0	0
T23	1053	0	0	0
T26	0	2	0	0
T28	0	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	2259	0	0
T1	3286	9	0	0
T2	2229	0	0	0
T3	1019	0	0	0
T4	13598	0	0	0
T5	25804	102	0	0
T6	1121	0	0	0
T7	964	0	0	0
T8	1872	0	0	0
T10	1113	0	0	0
T11	2378	0	0	0
T26	0	76	0	0
T30	0	52	0	0
T60	0	5	0	0
T61	0	105	0	0
T62	0	63	0	0
T63	0	10	0	0
T64	0	108	0	0
T65	0	44	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	3203	0	0
T1	3286	20	0	0
T2	2229	1	0	0
T3	1019	0	0	0
T4	13598	0	0	0
T5	25804	195	0	0
T6	1121	0	0	0
T7	964	0	0	0
T8	1872	8	0	0
T10	1113	13	0	0
T11	2378	0	0	0
T26	0	70	0	0
T30	0	113	0	0
T60	0	19	0	0
T66	0	14	0	0
T67	0	3	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	2260	0	0
T1	3286	10	0	0
T2	2229	6	0	0
T3	1019	0	0	0
T4	13598	0	0	0
T5	25804	77	0	0
T6	1121	0	0	0
T7	964	0	0	0
T8	1872	0	0	0
T10	1113	0	0	0
T11	2378	0	0	0
T26	0	42	0	0
T30	0	41	0	0
T60	0	4	0	0
T61	0	229	0	0
T62	0	37	0	0
T63	0	1	0	0
T64	0	202	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	2419	0	0
T1	3286	8	0	0
T2	2229	3	0	0
T3	1019	0	0	0
T4	13598	0	0	0
T5	25804	82	0	0
T6	1121	0	0	0
T7	964	0	0	0
T8	1872	0	0	0
T10	1113	0	0	0
T11	2378	0	0	0
T26	0	33	0	0
T30	0	60	0	0
T61	0	254	0	0
T62	0	91	0	0
T63	0	7	0	0
T64	0	243	0	0
T65	0	17	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	2100	0	0
T1	3286	6	0	0
T2	2229	4	0	0
T3	1019	0	0	0
T4	13598	0	0	0
T5	25804	77	0	0
T6	1121	0	0	0
T7	964	0	0	0
T8	1872	0	0	0
T10	1113	0	0	0
T11	2378	0	0	0
T26	0	16	0	0
T30	0	31	0	0
T60	0	6	0	0
T61	0	189	0	0
T62	0	49	0	0
T64	0	240	0	0
T65	0	33	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	2122	0	0
T1	3286	16	0	0
T2	2229	2	0	0
T3	1019	0	0	0
T4	13598	0	0	0
T5	25804	90	0	0
T6	1121	0	0	0
T7	964	0	0	0
T8	1872	0	0	0
T10	1113	0	0	0
T11	2378	0	0	0
T26	0	29	0	0
T30	0	44	0	0
T60	0	2	0	0
T61	0	225	0	0
T62	0	13	0	0
T63	0	7	0	0
T64	0	229	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	2310	0	0
T1	3286	7	0	0
T2	2229	7	0	0
T3	1019	0	0	0
T4	13598	0	0	0
T5	25804	79	0	0
T6	1121	0	0	0
T7	964	0	0	0
T8	1872	0	0	0
T10	1113	0	0	0
T11	2378	0	0	0
T18	0	4	0	0
T26	0	43	0	0
T30	0	35	0	0
T60	0	1	0	0
T61	0	225	0	0
T62	0	93	0	0
T64	0	178	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	2185	0	0
T1	3286	12	0	0
T2	2229	7	0	0
T3	1019	0	0	0
T4	13598	0	0	0
T5	25804	87	0	0
T6	1121	0	0	0
T7	964	0	0	0
T8	1872	0	0	0
T10	1113	0	0	0
T11	2378	0	0	0
T26	0	59	0	0
T30	0	38	0	0
T31	0	5	0	0
T60	0	4	0	0
T61	0	212	0	0
T62	0	14	0	0
T63	0	25	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	2225	0	0
T1	3286	7	0	0
T2	2229	3	0	0
T3	1019	0	0	0
T4	13598	0	0	0
T5	25804	80	0	0
T6	1121	0	0	0
T7	964	0	0	0
T8	1872	0	0	0
T10	1113	0	0	0
T11	2378	0	0	0
T26	0	40	0	0
T30	0	40	0	0
T60	0	3	0	0
T61	0	188	0	0
T62	0	64	0	0
T63	0	9	0	0
T64	0	244	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	2022	0	0
T1	3286	6	0	0
T2	2229	3	0	0
T3	1019	0	0	0
T4	13598	0	0	0
T5	25804	60	0	0
T6	1121	0	0	0
T7	964	0	0	0
T8	1872	0	0	0
T10	1113	0	0	0
T11	2378	0	0	0
T26	0	17	0	0
T30	0	59	0	0
T60	0	5	0	0
T61	0	222	0	0
T62	0	27	0	0
T63	0	19	0	0
T64	0	254	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	2243	0	0
T1	3286	17	0	0
T2	2229	4	0	0
T3	1019	0	0	0
T4	13598	0	0	0
T5	25804	79	0	0
T6	1121	0	0	0
T7	964	0	0	0
T8	1872	0	0	0
T10	1113	0	0	0
T11	2378	0	0	0
T26	0	39	0	0
T30	0	32	0	0
T60	0	8	0	0
T61	0	208	0	0
T62	0	24	0	0
T63	0	3	0	0
T64	0	196	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	2322	0	0
T1	3286	9	0	0
T2	2229	6	0	0
T3	1019	0	0	0
T4	13598	0	0	0
T5	25804	94	0	0
T6	1121	0	0	0
T7	964	0	0	0
T8	1872	0	0	0
T10	1113	0	0	0
T11	2378	0	0	0
T26	0	43	0	0
T30	0	42	0	0
T60	0	4	0	0
T61	0	204	0	0
T62	0	42	0	0
T63	0	15	0	0
T64	0	269	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1399749	2173	0	0
T1	3286	5	0	0
T2	2229	0	0	0
T3	1019	0	0	0
T4	13598	0	0	0
T5	25804	95	0	0
T6	1121	0	0	0
T7	964	0	0	0
T8	1872	0	0	0
T10	1113	0	0	0
T11	2378	0	0	0
T26	0	38	0	0
T30	0	40	0	0
T60	0	2	0	0
T61	0	226	0	0
T62	0	48	0	0
T63	0	7	0	0
T64	0	232	0	0
T68	0	2	0	0