Unified Coverage Report :: Module :: sha3pad

Module : sha3pad

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_pad	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_sha3.u_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prefix_slicer	0.00	0.00
u_sentmsg_count	0.00			0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
TOTAL		162	0	0.00
ALWAYS	157	6	0	0.00
CONT_ASSIGN	208	1	0	0.00
CONT_ASSIGN	212	1	0	0.00
CONT_ASSIGN	235	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	246	1	0	0.00
CONT_ASSIGN	256	1	0	0.00
ALWAYS	266	6	0	0.00
ALWAYS	278	3	0	0.00
CONT_ASSIGN	285	1	0	0.00
ALWAYS	292	3	0	0.00
ALWAYS	297	76	0	0.00
CONT_ASSIGN	508	1	0	0.00
CONT_ASSIGN	519	1	0	0.00
CONT_ASSIGN	540	1	0	0.00
ALWAYS	557	4	0	0.00
CONT_ASSIGN	580	1	0	0.00
CONT_ASSIGN	587	1	0	0.00
ALWAYS	590	5	0	0.00
ALWAYS	602	5	0	0.00
ALWAYS	614	5	0	0.00
ALWAYS	663	10	0	0.00
ALWAYS	718	9	0	0.00
ALWAYS	778	6	0	0.00
ALWAYS	787	6	0	0.00
ALWAYS	797	6	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	0	1
158	0	1
159	0	1
160	0	1
161	0	1
162	0	1
208	0	1
212	0	1
235	0	1
241	0	1
246	0	1
256	0	1
266	0	1
267	0	1
268	0	1
269	0	1
270	0	1
271	0	1
			==> MISSING_ELSE
278	0	3
285	0	1
292	0	2
293	0	1
297	0	1
300	0	1
301	0	1
303	0	1
305	0	1
306	0	1
308	0	1
309	0	1
311	0	1
313	0	1
315	0	1
324	0	1
326	0	1
327	0	1
329	0	1
332	0	1
344	0	1
346	0	1
347	0	1
349	0	1
350	0	1
351	0	1
353	0	1
355	0	1
360	0	1
362	0	1
363	0	1
365	0	1
374	0	1
376	0	1
377	0	1
379	0	1
380	0	1
382	0	1
384	0	1
385	0	1
386	0	1
387	0	1
388	0	1
391	0	1
393	0	1
399	0	1
401	0	1
402	0	1
404	0	1
413	0	1
415	0	1
417	0	1
420	0	1
423	0	1
424	0	1
425	0	1
426	0	1
427	0	1
429	0	1
434	0	1
436	0	1
437	0	1
446	0	1
450	0	1
451	0	1
453	0	1
454	0	1
455	0	1
457	0	1
459	0	1
465	0	1
466	0	1
468	0	1
469	0	1
471	0	1
473	0	1
479	0	1
480	0	1
493	0	1
494	0	1
			==> MISSING_ELSE
508	0	1
519	0	1
540	0	1
557	0	1
558	0	1
559	0	1
560	0	1
580	0	1
587	0	1
590	0	1
591	0	1
592	0	1
593	0	1
594	0	1
602	0	1
603	0	1
604	0	1
605	0	1
606	0	1
614	0	1
615	0	1
616	0	1
617	0	1
618	0	1
663	0	1
664	0	1
665	0	1
666	0	1
667	0	1
668	0	1
670	0	1
671	0	1
672	0	1
673	0	1
			==> MISSING_ELSE
718	0	1
719	0	1
720	0	1
721	0	1
722	0	1
723	0	1
724	0	1
725	0	1
726	0	1
778	0	1
779	0	1
780	0	1
781	0	1
782	0	1
783	0	1
			==> MISSING_ELSE
787	0	1
788	0	1
789	0	1
790	0	1
791	0	1
792	0	1
			==> MISSING_ELSE
797	0	1
798	0	1
799	0	1
800	0	1
801	0	1
802	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : sha3pad

	Total	Covered	Percent
Conditions	43	0	0.00
Logical	43	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       212
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       235
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       235
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       241
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       241
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       246
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       256
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       285
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       285
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       376
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       387
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       417
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       587
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       603
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       615
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       615
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

FSM Coverage for Module : sha3pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	0	0.00	(Not included in score)
Transitions	21	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	329	Not Covered
StMessageWait	382	Not Covered
StPad	388	Not Covered
StPad01	426	Not Covered
StPadFlush	434	Not Covered
StPadIdle	332	Not Covered
StPadRun	420	Not Covered
StPrefix	327	Not Covered
StPrefixWait	347	Not Covered
StTerminalError	494	Not Covered

transitions	Line No.	Covered	Tests
StMessage->StMessageWait	382	Not Covered
StMessage->StPad	388	Not Covered
StMessage->StTerminalError	494	Not Covered
StMessageWait->StMessage	402	Not Covered
StMessageWait->StTerminalError	494	Not Covered
StPad->StPad01	426	Not Covered
StPad->StPadRun	420	Not Covered
StPad->StTerminalError	494	Not Covered
StPad01->StPadFlush	451	Not Covered
StPad01->StTerminalError	494	Not Covered
StPadFlush->StPadIdle	469	Not Covered
StPadFlush->StTerminalError	494	Not Covered
StPadIdle->StMessage	329	Not Covered
StPadIdle->StPrefix	327	Not Covered
StPadIdle->StTerminalError	494	Not Covered
StPadRun->StPadFlush	434	Not Covered
StPadRun->StTerminalError	494	Not Covered
StPrefix->StPrefixWait	347	Not Covered
StPrefix->StTerminalError	494	Not Covered
StPrefixWait->StMessage	363	Not Covered
StPrefixWait->StTerminalError	494	Not Covered

---

Branch Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
Branches		93	0	0.00
TERNARY	212	2	0	0.00
TERNARY	235	2	0	0.00
TERNARY	241	2	0	0.00
TERNARY	285	2	0	0.00
TERNARY	587	2	0	0.00
CASE	157	6	0	0.00
IF	266	4	0	0.00
IF	278	2	0	0.00
IF	292	2	0	0.00
CASE	315	23	0	0.00
IF	493	2	0	0.00
CASE	557	4	0	0.00
CASE	590	5	0	0.00
CASE	602	5	0	0.00
CASE	614	5	0	0.00
IF	663	4	0	0.00
IF	778	4	0	0.00
IF	787	4	0	0.00
IF	797	4	0	0.00
CASE	718	9	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	235	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	241	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	285	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	587	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Not Covered
L224	Not Covered
L256	Not Covered
L384	Not Covered
L512	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if (process_i)
-3-:	270	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	278	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	292	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	315	case (st)
-2-:	324	if (start_i)
-3-:	326	if (mode_eq_cshake)
-4-:	346	if (sent_blocksize)
-5-:	362	if (keccak_complete_i)
-6-:	376	if ((msg_valid_i && msg_partial))
-7-:	380	if (sent_blocksize)
-8-:	387	if ((process_latched || process_i))
-9-:	401	if (keccak_complete_i)
-10-:	417	if ((keccak_ack && end_of_block))
-11-:	425	if (keccak_ack)
-12-:	450	if (sent_blocksize)
-13-:	468	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Not Covered
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Not Covered
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Not Covered
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Not Covered
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	493	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	557	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Not Covered
Shake	Not Covered
CShake	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	590	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Not Covered
MuxPrefix	Not Covered
MuxFuncPad	Not Covered
MuxZeroEnd	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	602	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Not Covered
MuxPrefix	Not Covered
MuxFuncPad	Not Covered
MuxZeroEnd	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	614	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Not Covered
MuxPrefix	Not Covered
MuxFuncPad	Not Covered
MuxZeroEnd	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	663	if ((!rst_ni))
-2-:	666	if (en_msgbuf)
-3-:	671	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	778	if ((!rst_ni))
-2-:	780	if (start_i)
-3-:	782	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	787	if ((!rst_ni))
-2-:	789	if (start_i)
-3-:	791	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	797	if ((!rst_ni))
-2-:	799	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	801	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	718	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Not Covered
7'b0000001	Not Covered
7'b0000011	Not Covered
7'b0000111	Not Covered
7'b0001111	Not Covered
7'b0011111	Not Covered
7'b0111111	Not Covered
7'b1111111	Not Covered
default	Not Covered

Line Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
TOTAL		162	0	0.00
ALWAYS	157	6	0	0.00
CONT_ASSIGN	208	1	0	0.00
CONT_ASSIGN	212	1	0	0.00
CONT_ASSIGN	235	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	246	1	0	0.00
CONT_ASSIGN	256	1	0	0.00
ALWAYS	266	6	0	0.00
ALWAYS	278	3	0	0.00
CONT_ASSIGN	285	1	0	0.00
ALWAYS	292	3	0	0.00
ALWAYS	297	76	0	0.00
CONT_ASSIGN	508	1	0	0.00
CONT_ASSIGN	519	1	0	0.00
CONT_ASSIGN	540	1	0	0.00
ALWAYS	557	4	0	0.00
CONT_ASSIGN	580	1	0	0.00
CONT_ASSIGN	587	1	0	0.00
ALWAYS	590	5	0	0.00
ALWAYS	602	5	0	0.00
ALWAYS	614	5	0	0.00
ALWAYS	663	10	0	0.00
ALWAYS	718	9	0	0.00
ALWAYS	778	6	0	0.00
ALWAYS	787	6	0	0.00
ALWAYS	797	6	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	0	1
158	0	1
159	0	1
160	0	1
161	0	1
162	0	1
208	0	1
212	0	1
235	0	1
241	0	1
246	0	1
256	0	1
266	0	1
267	0	1
268	0	1
269	0	1
270	0	1
271	0	1
			==> MISSING_ELSE
278	0	3
285	0	1
292	0	2
293	0	1
297	0	1
300	0	1
301	0	1
303	0	1
305	0	1
306	0	1
308	0	1
309	0	1
311	0	1
313	0	1
315	0	1
324	0	1
326	0	1
327	0	1
329	0	1
332	0	1
344	0	1
346	0	1
347	0	1
349	0	1
350	0	1
351	0	1
353	0	1
355	0	1
360	0	1
362	0	1
363	0	1
365	0	1
374	0	1
376	0	1
377	0	1
379	0	1
380	0	1
382	0	1
384	0	1
385	0	1
386	0	1
387	0	1
388	0	1
391	0	1
393	0	1
399	0	1
401	0	1
402	0	1
404	0	1
413	0	1
415	0	1
417	0	1
420	0	1
423	0	1
424	0	1
425	0	1
426	0	1
427	0	1
429	0	1
434	0	1
436	0	1
437	0	1
446	0	1
450	0	1
451	0	1
453	0	1
454	0	1
455	0	1
457	0	1
459	0	1
465	0	1
466	0	1
468	0	1
469	0	1
471	0	1
473	0	1
479	0	1
480	0	1
493	0	1
494	0	1
			==> MISSING_ELSE
508	0	1
519	0	1
540	0	1
557	0	1
558	0	1
559	0	1
560	0	1
580	0	1
587	0	1
590	0	1
591	0	1
592	0	1
593	0	1
594	0	1
602	0	1
603	0	1
604	0	1
605	0	1
606	0	1
614	0	1
615	0	1
616	0	1
617	0	1
618	0	1
663	0	1
664	0	1
665	0	1
666	0	1
667	0	1
668	0	1
670	0	1
671	0	1
672	0	1
673	0	1
			==> MISSING_ELSE
718	0	1
719	0	1
720	0	1
721	0	1
722	0	1
723	0	1
724	0	1
725	0	1
726	0	1
778	0	1
779	0	1
780	0	1
781	0	1
782	0	1
783	0	1
			==> MISSING_ELSE
787	0	1
788	0	1
789	0	1
790	0	1
791	0	1
792	0	1
			==> MISSING_ELSE
797	0	1
798	0	1
799	0	1
800	0	1
801	0	1
802	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Covered	Percent
Conditions	43	0	0.00
Logical	43	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       212
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       235
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       235
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       241
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       241
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       246
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       256
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       285
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       285
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       376
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       387
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       417
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       587
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       603
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       615
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       615
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_sha3.u_pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	0	0.00	(Not included in score)
Transitions	17	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	329	Not Covered
StMessageWait	382	Not Covered
StPad	388	Not Covered
StPad01	426	Not Covered
StPadFlush	434	Not Covered
StPadIdle	332	Not Covered
StPadRun	420	Not Covered
StPrefix	327	Not Covered
StPrefixWait	347	Not Covered
StTerminalError	494	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
StMessage->StMessageWait	382	Not Covered
StMessage->StPad	388	Not Covered
StMessage->StTerminalError	494	Not Covered
StMessageWait->StMessage	402	Not Covered
StMessageWait->StTerminalError	494	Not Covered
StPad->StPad01	426	Not Covered
StPad->StPadRun	420	Not Covered
StPad->StTerminalError	494	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPad01->StPadFlush	451	Not Covered
StPad01->StTerminalError	494	Not Covered
StPadFlush->StPadIdle	469	Not Covered
StPadFlush->StTerminalError	494	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPadIdle->StMessage	329	Not Covered
StPadIdle->StPrefix	327	Not Covered
StPadIdle->StTerminalError	494	Not Covered
StPadRun->StPadFlush	434	Not Covered
StPadRun->StTerminalError	494	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefix->StPrefixWait	347	Not Covered
StPrefix->StTerminalError	494	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefixWait->StMessage	363	Not Covered
StPrefixWait->StTerminalError	494	Not Covered

---

Branch Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
Branches		93	0	0.00
TERNARY	212	2	0	0.00
TERNARY	235	2	0	0.00
TERNARY	241	2	0	0.00
TERNARY	285	2	0	0.00
TERNARY	587	2	0	0.00
CASE	157	6	0	0.00
IF	266	4	0	0.00
IF	278	2	0	0.00
IF	292	2	0	0.00
CASE	315	23	0	0.00
IF	493	2	0	0.00
CASE	557	4	0	0.00
CASE	590	5	0	0.00
CASE	602	5	0	0.00
CASE	614	5	0	0.00
IF	663	4	0	0.00
IF	778	4	0	0.00
IF	787	4	0	0.00
IF	797	4	0	0.00
CASE	718	9	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	235	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	241	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	285	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	587	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Not Covered
L224	Not Covered
L256	Not Covered
L384	Not Covered
L512	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if (process_i)
-3-:	270	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	278	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	292	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	315	case (st)
-2-:	324	if (start_i)
-3-:	326	if (mode_eq_cshake)
-4-:	346	if (sent_blocksize)
-5-:	362	if (keccak_complete_i)
-6-:	376	if ((msg_valid_i && msg_partial))
-7-:	380	if (sent_blocksize)
-8-:	387	if ((process_latched || process_i))
-9-:	401	if (keccak_complete_i)
-10-:	417	if ((keccak_ack && end_of_block))
-11-:	425	if (keccak_ack)
-12-:	450	if (sent_blocksize)
-13-:	468	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Not Covered
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Not Covered
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Not Covered
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Not Covered
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	493	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	557	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Not Covered
Shake	Not Covered
CShake	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	590	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Not Covered
MuxPrefix	Not Covered
MuxFuncPad	Not Covered
MuxZeroEnd	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	602	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Not Covered
MuxPrefix	Not Covered
MuxFuncPad	Not Covered
MuxZeroEnd	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	614	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Not Covered
MuxPrefix	Not Covered
MuxFuncPad	Not Covered
MuxZeroEnd	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	663	if ((!rst_ni))
-2-:	666	if (en_msgbuf)
-3-:	671	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	778	if ((!rst_ni))
-2-:	780	if (start_i)
-3-:	782	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	787	if ((!rst_ni))
-2-:	789	if (start_i)
-3-:	791	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	797	if ((!rst_ni))
-2-:	799	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	801	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	718	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Not Covered
7'b0000001	Not Covered
7'b0000011	Not Covered
7'b0000111	Not Covered
7'b0001111	Not Covered
7'b0011111	Not Covered
7'b0111111	Not Covered
7'b1111111	Not Covered
default	Not Covered