Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	259644107	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

207360039

1

T1

80

T2

640

T3

1239

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	245469046	1			T1	25		T2	321		T3	619
values[0x0]	106273214	1			T1	39		T2	148		T3	299
values[0x1]	115261886	1			T1	41		T2	171		T3	322

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202109351	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

264894795

1

T1

97

T2

640

T3

1239

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3467701	1			T1	1		T3	4		T55	9
valid_sources[0x01]	2784068	1			T2	2		T3	1		T55	20
valid_sources[0x02]	1645888	1			T2	1		T55	38		T52	3
valid_sources[0x03]	1418639	1			T2	2		T55	34		T52	3
valid_sources[0x04]	1421615	1			T55	8		T52	1		T58	1
valid_sources[0x05]	1786369	1			T2	6		T3	11		T55	35
valid_sources[0x06]	3639623	1			T55	40		T56	1		T52	6
valid_sources[0x07]	1875870	1			T2	3		T55	51		T51	1
valid_sources[0x08]	3451084	1			T2	6		T55	29		T52	2
valid_sources[0x09]	1411087	1			T55	45		T52	6		T53	3
valid_sources[0x0a]	1416530	1			T2	3		T52	3		T58	6
valid_sources[0x0b]	1408469	1			T55	46		T56	1		T52	9
valid_sources[0x0c]	1876868	1			T2	6		T3	30		T55	5
valid_sources[0x0d]	1515670	1			T2	2		T55	23		T51	1
valid_sources[0x0e]	1416454	1			T1	1		T2	7		T55	59
valid_sources[0x0f]	1403355	1			T2	2		T3	10		T55	19
valid_sources[0x10]	1412941	1			T2	8		T55	32		T52	1
valid_sources[0x11]	2499179	1			T1	1		T2	1		T3	9
valid_sources[0x12]	2076364	1			T2	2		T3	5		T55	32
valid_sources[0x13]	1480415	1			T2	4		T55	7		T52	12
valid_sources[0x14]	3931561	1			T2	4		T3	17		T55	6
valid_sources[0x15]	1413992	1			T55	38		T51	1		T52	13
valid_sources[0x16]	1739530	1			T2	1		T55	25		T52	18
valid_sources[0x17]	1468902	1			T55	22		T52	1		T58	3
valid_sources[0x18]	1407929	1			T55	22		T52	12		T58	2
valid_sources[0x19]	1418595	1			T2	1		T3	4		T55	21
valid_sources[0x1a]	1408958	1			T3	22		T55	42		T52	3
valid_sources[0x1b]	3466362	1			T2	12		T55	24		T56	1
valid_sources[0x1c]	1603661	1			T1	2		T3	8		T55	30
valid_sources[0x1d]	1401873	1			T2	1		T3	10		T55	26
valid_sources[0x1e]	1564378	1			T2	1		T3	23		T55	17
valid_sources[0x1f]	3999578	1			T2	3		T3	1		T55	29
valid_sources[0x20]	3125155	1			T55	40		T52	3		T53	1
valid_sources[0x21]	1412021	1			T55	40		T56	3		T58	1
valid_sources[0x22]	1415940	1			T2	1		T3	2		T55	35
valid_sources[0x23]	1414539	1			T2	15		T55	12		T52	7
valid_sources[0x24]	1440499	1			T3	22		T55	8		T51	1
valid_sources[0x25]	2526424	1			T2	5		T55	26		T52	12
valid_sources[0x26]	1416109	1			T55	28		T51	1		T52	3
valid_sources[0x27]	1412268	1			T1	2		T2	3		T3	4
valid_sources[0x28]	3562184	1			T2	4		T3	10		T55	24
valid_sources[0x29]	1415405	1			T2	9		T3	53		T55	44
valid_sources[0x2a]	2066362	1			T2	2		T55	28		T52	2
valid_sources[0x2b]	1416669	1			T1	1		T2	1		T3	24
valid_sources[0x2c]	3839166	1			T2	8		T55	31		T52	7
valid_sources[0x2d]	1409407	1			T2	2		T55	43		T56	1
valid_sources[0x2e]	1406003	1			T2	1		T3	4		T55	36
valid_sources[0x2f]	1417915	1			T2	4		T55	58		T52	6
valid_sources[0x30]	1412006	1			T55	23		T52	1		T58	1
valid_sources[0x31]	1416883	1			T3	7		T55	23		T52	3
valid_sources[0x32]	4736126	1			T2	2		T3	27		T55	27
valid_sources[0x33]	1404544	1			T1	2		T3	6		T55	42
valid_sources[0x34]	1409518	1			T55	12		T52	4		T58	3
valid_sources[0x35]	1417447	1			T2	3		T3	6		T55	45
valid_sources[0x36]	1522055	1			T1	1		T2	2		T3	54
valid_sources[0x37]	1417421	1			T1	1		T55	17		T51	1
valid_sources[0x38]	1412061	1			T2	2		T3	18		T55	36
valid_sources[0x39]	1536272	1			T2	5		T3	3		T55	71
valid_sources[0x3a]	1409955	1			T1	2		T2	1		T55	34
valid_sources[0x3b]	1414277	1			T3	5		T55	40		T52	3
valid_sources[0x3c]	1488126	1			T2	1		T55	21		T52	5
valid_sources[0x3d]	1592335	1			T2	5		T55	48		T52	3
valid_sources[0x3e]	1412401	1			T55	33		T52	11		T58	4
valid_sources[0x3f]	1410538	1			T2	2		T55	24		T53	1
valid_sources[0x40]	1416011	1			T3	3		T55	21		T53	11
valid_sources[0x41]	1415283	1			T3	2		T55	10		T52	7
valid_sources[0x42]	1527086	1			T2	2		T3	3		T55	28
valid_sources[0x43]	1417465	1			T55	25		T51	1		T52	10
valid_sources[0x44]	1410290	1			T2	3		T3	6		T55	21
valid_sources[0x45]	1413745	1			T3	10		T55	38		T52	4
valid_sources[0x46]	1515450	1			T3	18		T55	22		T52	13
valid_sources[0x47]	2250581	1			T2	4		T55	14		T51	2
valid_sources[0x48]	1549238	1			T2	5		T55	36		T52	1
valid_sources[0x49]	1409231	1			T3	16		T55	26		T52	3
valid_sources[0x4a]	1415530	1			T2	1		T3	7		T55	13
valid_sources[0x4b]	2309553	1			T2	1		T55	20		T51	1
valid_sources[0x4c]	1419408	1			T55	10		T52	4		T58	6
valid_sources[0x4d]	1415380	1			T55	20		T52	2		T58	2
valid_sources[0x4e]	1407889	1			T55	1		T52	8		T111	6
valid_sources[0x4f]	1460135	1			T2	4		T55	33		T52	6
valid_sources[0x50]	1425020	1			T3	12		T55	16		T51	1
valid_sources[0x51]	1413682	1			T2	1		T55	22		T52	2
valid_sources[0x52]	1412952	1			T2	7		T3	10		T55	10
valid_sources[0x53]	2325343	1			T2	3		T55	28		T52	3
valid_sources[0x54]	3858254	1			T2	3		T3	16		T55	8
valid_sources[0x55]	1421791	1			T2	3		T55	18		T52	1
valid_sources[0x56]	1414125	1			T1	2		T2	3		T3	8
valid_sources[0x57]	1596855	1			T2	5		T55	27		T52	5
valid_sources[0x58]	1503697	1			T55	18		T52	1		T58	5
valid_sources[0x59]	1408181	1			T2	2		T55	41		T52	7
valid_sources[0x5a]	1422532	1			T2	4		T3	1		T55	47
valid_sources[0x5b]	1418729	1			T2	1		T3	10		T55	5
valid_sources[0x5c]	1405893	1			T2	11		T55	29		T52	1
valid_sources[0x5d]	3435007	1			T1	1		T2	1		T3	15
valid_sources[0x5e]	1410512	1			T3	8		T55	46		T56	2
valid_sources[0x5f]	2177710	1			T2	6		T55	39		T52	4
valid_sources[0x60]	1420791	1			T1	6		T3	1		T55	45
valid_sources[0x61]	2027614	1			T2	1		T3	17		T55	22
valid_sources[0x62]	1417691	1			T2	6		T55	64		T52	14
valid_sources[0x63]	1417417	1			T1	3		T2	7		T3	18
valid_sources[0x64]	2082956	1			T2	3		T55	27		T52	2
valid_sources[0x65]	1417189	1			T3	7		T55	33		T52	4
valid_sources[0x66]	1410635	1			T55	19		T58	5		T111	4
valid_sources[0x67]	1544066	1			T3	3		T55	2		T51	2
valid_sources[0x68]	1437394	1			T1	2		T2	11		T55	19
valid_sources[0x69]	3851626	1			T1	1		T2	3		T55	37
valid_sources[0x6a]	1629803	1			T1	2		T3	8		T55	24
valid_sources[0x6b]	1901179	1			T2	10		T55	36		T52	2
valid_sources[0x6c]	1400964	1			T3	18		T55	20		T53	4
valid_sources[0x6d]	1503394	1			T2	6		T3	6		T55	23
valid_sources[0x6e]	2771175	1			T55	11		T52	5		T58	2
valid_sources[0x6f]	1434286	1			T2	3		T55	47		T52	13
valid_sources[0x70]	1403838	1			T2	4		T55	50		T59	1
valid_sources[0x71]	2154816	1			T2	1		T3	3		T55	33
valid_sources[0x72]	3817521	1			T2	2		T3	10		T55	31
valid_sources[0x73]	2330053	1			T1	12		T2	2		T3	1
valid_sources[0x74]	1464196	1			T2	3		T3	6		T55	52
valid_sources[0x75]	1416626	1			T3	8		T55	76		T52	6
valid_sources[0x76]	1410979	1			T3	9		T55	46		T51	4
valid_sources[0x77]	1406845	1			T55	12		T52	3		T58	2
valid_sources[0x78]	3938531	1			T1	1		T3	2		T55	11
valid_sources[0x79]	1417000	1			T2	3		T55	23		T56	1
valid_sources[0x7a]	1418394	1			T55	15		T52	2		T59	1
valid_sources[0x7b]	1578940	1			T2	1		T55	49		T52	2
valid_sources[0x7c]	1404128	1			T2	10		T55	20		T52	6
valid_sources[0x7d]	3823067	1			T2	5		T3	24		T55	44
valid_sources[0x7e]	1409217	1			T3	2		T55	68		T52	6
valid_sources[0x7f]	1412456	1			T2	1		T3	1		T55	7
valid_sources[0x80]	1399663	1			T1	9		T55	15		T52	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

89989853

1

T1

18

T2

321

T3

618

values[0x0]

all_enables

biggest_size

63052571

1

T1

37

T2

148

T3

299

values[0x1]

all_enables

biggest_size

54317615

1

T1

25

T2

171

T3

322