Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

267767209

1

T1

328

T3

1

T55

2108

full_word

207862971

1

T1

107

T2

640

T3

1239

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	475629910	1			T1	435		T2	640		T3	1240
auto[TlIntgErrCmd]	84	1			T102	6		T104	4		T105	3
auto[TlIntgErrData]	87	1			T102	7		T104	3		T105	4
auto[TlIntgErrBoth]	99	1			T102	7		T104	3		T105	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

247020335

1

T1

124

T2

321

T3

619

auto[1]

228609845

1

T1

311

T2

319

T3

621

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	156904118	1			T1	98		T3	1		T55	1830
auto[TlIntgErrNone]	partial	auto[1]	110862844	1			T1	230		T55	278		T56	16
auto[TlIntgErrNone]	full_word	auto[0]	90116090	1			T1	26		T2	321		T3	618
auto[TlIntgErrNone]	full_word	auto[1]	117746858	1			T1	81		T2	319		T3	621
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T102	2		T104	2		T105	2
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T102	4		T104	2		T105	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T148	1		T150	1		T151	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T109	1		T147	1		T148	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T102	1		T104	1		T105	1
auto[TlIntgErrData]	partial	auto[1]	36	1			T102	5		T104	1		T105	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T102	1		T104	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T152	1		T148	1		T150	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T102	2		T104	1		T105	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T102	5		T104	2		T105	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T112	1		T151	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T105	1		T107	3		T153	1