Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	118831138	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1274	1274	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	118831138	0	0
T1	4366	286	0	0
T2	4645	0	0	0
T3	9676	0	0	0
T51	1500	2	0	0
T52	11499	0	0	0
T53	3042	0	0	0
T54	0	320	0	0
T55	78184	0	0	0
T56	1056	0	0	0
T58	7796	0	0	0
T59	1201	0	0	0
T77	0	239	0	0
T78	0	254	0	0
T79	0	95	0	0
T80	0	521	0	0
T81	0	318	0	0
T82	0	387	0	0
T84	0	501	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4366	4316	0	0
T2	4645	4558	0	0
T3	9676	9625	0	0
T51	1500	1411	0	0
T52	11499	11343	0	0
T53	3042	2701	0	0
T55	78184	78084	0	0
T56	1056	981	0	0
T58	7796	7433	0	0
T59	1201	1118	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4366	4316	0	0
T2	4645	4558	0	0
T3	9676	9625	0	0
T51	1500	1411	0	0
T52	11499	11343	0	0
T53	3042	2701	0	0
T55	78184	78084	0	0
T56	1056	981	0	0
T58	7796	7433	0	0
T59	1201	1118	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4366	4316	0	0
T2	4645	4558	0	0
T3	9676	9625	0	0
T51	1500	1411	0	0
T52	11499	11343	0	0
T53	3042	2701	0	0
T55	78184	78084	0	0
T56	1056	981	0	0
T58	7796	7433	0	0
T59	1201	1118	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1274	1274	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	211899591	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1274	1274	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	211899591	0	0
T1	4366	646	0	0
T2	4645	0	0	0
T3	9676	0	0	0
T51	1500	2	0	0
T52	11499	0	0	0
T53	3042	0	0	0
T54	0	722	0	0
T55	78184	0	0	0
T56	1056	0	0	0
T58	7796	0	0	0
T59	1201	0	0	0
T77	0	236	0	0
T78	0	665	0	0
T79	0	326	0	0
T80	0	290	0	0
T81	0	1201	0	0
T82	0	236	0	0
T84	0	251	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4366	4316	0	0
T2	4645	4558	0	0
T3	9676	9625	0	0
T51	1500	1411	0	0
T52	11499	11343	0	0
T53	3042	2701	0	0
T55	78184	78084	0	0
T56	1056	981	0	0
T58	7796	7433	0	0
T59	1201	1118	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4366	4316	0	0
T2	4645	4558	0	0
T3	9676	9625	0	0
T51	1500	1411	0	0
T52	11499	11343	0	0
T53	3042	2701	0	0
T55	78184	78084	0	0
T56	1056	981	0	0
T58	7796	7433	0	0
T59	1201	1118	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4366	4316	0	0
T2	4645	4558	0	0
T3	9676	9625	0	0
T51	1500	1411	0	0
T52	11499	11343	0	0
T53	3042	2701	0	0
T55	78184	78084	0	0
T56	1056	981	0	0
T58	7796	7433	0	0
T59	1201	1118	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1274	1274	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	323614148	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1274	1274	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	323614148	0	0
T1	4366	231	0	0
T2	4645	697	0	0
T3	9676	2193	0	0
T51	1500	70	0	0
T52	11499	2818	0	0
T53	3042	361	0	0
T55	78184	7418	0	0
T56	1056	40	0	0
T58	7796	2070	0	0
T59	1201	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4366	4316	0	0
T2	4645	4558	0	0
T3	9676	9625	0	0
T51	1500	1411	0	0
T52	11499	11343	0	0
T53	3042	2701	0	0
T55	78184	78084	0	0
T56	1056	981	0	0
T58	7796	7433	0	0
T59	1201	1118	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4366	4316	0	0
T2	4645	4558	0	0
T3	9676	9625	0	0
T51	1500	1411	0	0
T52	11499	11343	0	0
T53	3042	2701	0	0
T55	78184	78084	0	0
T56	1056	981	0	0
T58	7796	7433	0	0
T59	1201	1118	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4366	4316	0	0
T2	4645	4558	0	0
T3	9676	9625	0	0
T51	1500	1411	0	0
T52	11499	11343	0	0
T53	3042	2701	0	0
T55	78184	78084	0	0
T56	1056	981	0	0
T58	7796	7433	0	0
T59	1201	1118	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1274	1274	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	593912929	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1274	1274	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	593912929	0	0
T1	4366	558	0	0
T2	4645	640	0	0
T3	9676	3696	0	0
T51	1500	63	0	0
T52	11499	5870	0	0
T53	3042	748	0	0
T55	78184	33123	0	0
T56	1056	40	0	0
T58	7796	3889	0	0
T59	1201	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4366	4316	0	0
T2	4645	4558	0	0
T3	9676	9625	0	0
T51	1500	1411	0	0
T52	11499	11343	0	0
T53	3042	2701	0	0
T55	78184	78084	0	0
T56	1056	981	0	0
T58	7796	7433	0	0
T59	1201	1118	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4366	4316	0	0
T2	4645	4558	0	0
T3	9676	9625	0	0
T51	1500	1411	0	0
T52	11499	11343	0	0
T53	3042	2701	0	0
T55	78184	78084	0	0
T56	1056	981	0	0
T58	7796	7433	0	0
T59	1201	1118	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4366	4316	0	0
T2	4645	4558	0	0
T3	9676	9625	0	0
T51	1500	1411	0	0
T52	11499	11343	0	0
T53	3042	2701	0	0
T55	78184	78084	0	0
T56	1056	981	0	0
T58	7796	7433	0	0
T59	1201	1118	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1274	1274	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0