Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	96.32	91.89	100.00	100.00	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1823993	0	0
entropy_period_rd_A	2147483647	2492	0	0
intr_enable_rd_A	2147483647	2926	0	0
prefix_0_rd_A	2147483647	2391	0	0
prefix_10_rd_A	2147483647	2248	0	0
prefix_1_rd_A	2147483647	2399	0	0
prefix_2_rd_A	2147483647	2333	0	0
prefix_3_rd_A	2147483647	2386	0	0
prefix_4_rd_A	2147483647	2290	0	0
prefix_5_rd_A	2147483647	2381	0	0
prefix_6_rd_A	2147483647	2183	0	0
prefix_7_rd_A	2147483647	2430	0	0
prefix_8_rd_A	2147483647	2340	0	0
prefix_9_rd_A	2147483647	2450	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1823993	0	0
T1	4366	54	0	0
T2	4645	0	0	0
T3	9676	0	0	0
T51	1500	1	0	0
T52	11499	0	0	0
T53	3042	0	0	0
T54	0	81	0	0
T55	78184	0	0	0
T56	1056	0	0	0
T58	7796	0	0	0
T59	1201	0	0	0
T77	0	223	0	0
T78	0	254	0	0
T80	0	17	0	0
T81	0	140	0	0
T104	0	1	0	0
T105	0	1	0	0
T109	0	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2492	0	0
T3	9676	23	0	0
T51	1500	0	0	0
T52	11499	90	0	0
T53	3042	14	0	0
T55	78184	108	0	0
T56	1056	0	0	0
T58	7796	50	0	0
T59	1201	0	0	0
T87	3013	0	0	0
T99	0	78	0	0
T111	9508	0	0	0
T114	0	4	0	0
T115	0	17	0	0
T126	0	13	0	0
T129	0	111	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2926	0	0
T3	9676	43	0	0
T51	1500	0	0	0
T52	11499	88	0	0
T53	3042	14	0	0
T55	78184	207	0	0
T56	1056	0	0	0
T58	7796	35	0	0
T59	1201	0	0	0
T87	3013	0	0	0
T111	9508	0	0	0
T114	0	11	0	0
T115	0	6	0	0
T126	0	50	0	0
T129	0	120	0	0
T130	0	16	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2391	0	0
T3	9676	18	0	0
T51	1500	0	0	0
T52	11499	40	0	0
T53	3042	12	0	0
T55	78184	250	0	0
T56	1056	0	0	0
T58	7796	43	0	0
T59	1201	0	0	0
T87	3013	0	0	0
T99	0	51	0	0
T111	9508	0	0	0
T114	0	5	0	0
T115	0	8	0	0
T126	0	28	0	0
T129	0	119	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2248	0	0
T3	9676	9	0	0
T51	1500	0	0	0
T52	11499	44	0	0
T53	3042	9	0	0
T55	78184	239	0	0
T56	1056	0	0	0
T58	7796	15	0	0
T59	1201	0	0	0
T87	3013	0	0	0
T99	0	40	0	0
T111	9508	0	0	0
T114	0	10	0	0
T115	0	21	0	0
T126	0	8	0	0
T129	0	110	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2399	0	0
T3	9676	5	0	0
T51	1500	0	0	0
T52	11499	49	0	0
T53	3042	8	0	0
T55	78184	218	0	0
T56	1056	0	0	0
T58	7796	29	0	0
T59	1201	0	0	0
T87	3013	0	0	0
T99	0	48	0	0
T111	9508	0	0	0
T114	0	7	0	0
T115	0	9	0	0
T126	0	24	0	0
T129	0	134	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2333	0	0
T3	9676	16	0	0
T51	1500	0	0	0
T52	11499	28	0	0
T53	3042	6	0	0
T55	78184	230	0	0
T56	1056	0	0	0
T58	7796	41	0	0
T59	1201	0	0	0
T87	3013	0	0	0
T99	0	33	0	0
T111	9508	0	0	0
T114	0	5	0	0
T115	0	16	0	0
T126	0	41	0	0
T129	0	84	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2386	0	0
T3	9676	25	0	0
T51	1500	0	0	0
T52	11499	43	0	0
T53	3042	9	0	0
T55	78184	210	0	0
T56	1056	0	0	0
T58	7796	32	0	0
T59	1201	0	0	0
T87	3013	0	0	0
T99	0	50	0	0
T111	9508	0	0	0
T114	0	6	0	0
T116	0	14	0	0
T126	0	25	0	0
T129	0	148	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2290	0	0
T3	9676	17	0	0
T51	1500	0	0	0
T52	11499	39	0	0
T53	3042	9	0	0
T55	78184	237	0	0
T56	1056	0	0	0
T58	7796	28	0	0
T59	1201	0	0	0
T87	3013	0	0	0
T99	0	40	0	0
T111	9508	0	0	0
T114	0	9	0	0
T115	0	9	0	0
T126	0	53	0	0
T129	0	123	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2381	0	0
T3	9676	20	0	0
T51	1500	0	0	0
T52	11499	57	0	0
T53	3042	2	0	0
T55	78184	200	0	0
T56	1056	0	0	0
T58	7796	39	0	0
T59	1201	0	0	0
T87	3013	0	0	0
T99	0	59	0	0
T111	9508	0	0	0
T114	0	11	0	0
T115	0	5	0	0
T126	0	72	0	0
T129	0	100	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2183	0	0
T3	9676	13	0	0
T51	1500	0	0	0
T52	11499	42	0	0
T53	3042	12	0	0
T55	78184	206	0	0
T56	1056	0	0	0
T58	7796	43	0	0
T59	1201	0	0	0
T87	3013	0	0	0
T99	0	43	0	0
T111	9508	0	0	0
T115	0	46	0	0
T116	0	7	0	0
T126	0	26	0	0
T129	0	123	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2430	0	0
T3	9676	35	0	0
T51	1500	0	0	0
T52	11499	53	0	0
T53	3042	14	0	0
T54	0	5	0	0
T55	78184	206	0	0
T56	1056	0	0	0
T58	7796	28	0	0
T59	1201	0	0	0
T87	3013	0	0	0
T111	9508	0	0	0
T114	0	7	0	0
T115	0	10	0	0
T126	0	63	0	0
T129	0	130	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2340	0	0
T3	9676	29	0	0
T51	1500	0	0	0
T52	11499	42	0	0
T53	3042	17	0	0
T55	78184	241	0	0
T56	1056	0	0	0
T58	7796	28	0	0
T59	1201	0	0	0
T87	3013	0	0	0
T99	0	53	0	0
T111	9508	0	0	0
T114	0	14	0	0
T115	0	12	0	0
T126	0	29	0	0
T129	0	119	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2450	0	0
T3	9676	15	0	0
T51	1500	0	0	0
T52	11499	37	0	0
T53	3042	9	0	0
T55	78184	192	0	0
T56	1056	0	0	0
T58	7796	43	0	0
T59	1201	0	0	0
T87	3013	0	0	0
T99	0	42	0	0
T111	9508	0	0	0
T114	0	17	0	0
T116	0	8	0	0
T126	0	26	0	0
T129	0	122	0	0