Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	96.32	91.89	100.00	100.00	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	943556	0	0
entropy_period_rd_A	2147483647	2550	0	0
intr_enable_rd_A	2147483647	3141	0	0
prefix_0_rd_A	2147483647	2641	0	0
prefix_10_rd_A	2147483647	2492	0	0
prefix_1_rd_A	2147483647	2557	0	0
prefix_2_rd_A	2147483647	2600	0	0
prefix_3_rd_A	2147483647	2472	0	0
prefix_4_rd_A	2147483647	2669	0	0
prefix_5_rd_A	2147483647	2546	0	0
prefix_6_rd_A	2147483647	2561	0	0
prefix_7_rd_A	2147483647	2696	0	0
prefix_8_rd_A	2147483647	2634	0	0
prefix_9_rd_A	2147483647	2564	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	943556	0	0
T6	1951	0	0	0
T9	3935	0	0	0
T25	127447	91747	0	0
T26	0	40709	0	0
T29	494257	0	0	0
T30	185983	0	0	0
T37	889986	0	0	0
T40	0	15695	0	0
T46	136564	0	0	0
T47	6173	0	0	0
T48	135601	0	0	0
T49	862593	0	0	0
T102	0	87568	0	0
T103	0	65110	0	0
T104	0	29700	0	0
T105	0	54219	0	0
T106	0	87904	0	0
T107	0	83929	0	0
T108	0	82662	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2550	0	0
T79	0	17	0	0
T105	736105	149	0	0
T125	0	223	0	0
T126	0	9	0	0
T127	0	24	0	0
T128	0	30	0	0
T129	0	14	0	0
T130	0	16	0	0
T131	0	247	0	0
T132	0	48	0	0
T133	986	0	0	0
T134	651270	0	0	0
T135	705941	0	0	0
T136	647871	0	0	0
T137	16771	0	0	0
T138	604368	0	0	0
T139	115142	0	0	0
T140	662531	0	0	0
T141	108303	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3141	0	0
T79	0	18	0	0
T99	0	6	0	0
T100	0	6	0	0
T105	736105	73	0	0
T125	0	183	0	0
T126	0	17	0	0
T127	0	4	0	0
T128	0	55	0	0
T129	0	25	0	0
T133	986	0	0	0
T134	651270	0	0	0
T135	705941	0	0	0
T136	647871	0	0	0
T137	16771	0	0	0
T138	604368	0	0	0
T139	115142	0	0	0
T140	662531	0	0	0
T141	108303	0	0	0
T142	0	10	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2641	0	0
T79	0	13	0	0
T105	736105	112	0	0
T125	0	208	0	0
T126	0	16	0	0
T127	0	8	0	0
T128	0	33	0	0
T129	0	18	0	0
T130	0	20	0	0
T131	0	223	0	0
T132	0	28	0	0
T133	986	0	0	0
T134	651270	0	0	0
T135	705941	0	0	0
T136	647871	0	0	0
T137	16771	0	0	0
T138	604368	0	0	0
T139	115142	0	0	0
T140	662531	0	0	0
T141	108303	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2492	0	0
T79	0	6	0	0
T105	736105	141	0	0
T125	0	242	0	0
T126	0	5	0	0
T127	0	13	0	0
T128	0	47	0	0
T129	0	13	0	0
T130	0	1	0	0
T131	0	214	0	0
T132	0	8	0	0
T133	986	0	0	0
T134	651270	0	0	0
T135	705941	0	0	0
T136	647871	0	0	0
T137	16771	0	0	0
T138	604368	0	0	0
T139	115142	0	0	0
T140	662531	0	0	0
T141	108303	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2557	0	0
T79	0	2	0	0
T105	736105	137	0	0
T125	0	252	0	0
T126	0	3	0	0
T127	0	8	0	0
T128	0	62	0	0
T129	0	26	0	0
T130	0	14	0	0
T131	0	273	0	0
T132	0	30	0	0
T133	986	0	0	0
T134	651270	0	0	0
T135	705941	0	0	0
T136	647871	0	0	0
T137	16771	0	0	0
T138	604368	0	0	0
T139	115142	0	0	0
T140	662531	0	0	0
T141	108303	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2600	0	0
T79	0	23	0	0
T105	736105	115	0	0
T125	0	220	0	0
T126	0	5	0	0
T127	0	19	0	0
T128	0	65	0	0
T129	0	8	0	0
T130	0	1	0	0
T131	0	190	0	0
T132	0	45	0	0
T133	986	0	0	0
T134	651270	0	0	0
T135	705941	0	0	0
T136	647871	0	0	0
T137	16771	0	0	0
T138	604368	0	0	0
T139	115142	0	0	0
T140	662531	0	0	0
T141	108303	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2472	0	0
T79	0	25	0	0
T105	736105	81	0	0
T125	0	240	0	0
T126	0	15	0	0
T127	0	12	0	0
T128	0	23	0	0
T129	0	18	0	0
T130	0	2	0	0
T131	0	216	0	0
T132	0	22	0	0
T133	986	0	0	0
T134	651270	0	0	0
T135	705941	0	0	0
T136	647871	0	0	0
T137	16771	0	0	0
T138	604368	0	0	0
T139	115142	0	0	0
T140	662531	0	0	0
T141	108303	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2669	0	0
T79	0	17	0	0
T105	736105	149	0	0
T125	0	240	0	0
T127	0	12	0	0
T128	0	58	0	0
T129	0	21	0	0
T130	0	31	0	0
T131	0	245	0	0
T132	0	31	0	0
T133	986	0	0	0
T134	651270	0	0	0
T135	705941	0	0	0
T136	647871	0	0	0
T137	16771	0	0	0
T138	604368	0	0	0
T139	115142	0	0	0
T140	662531	0	0	0
T141	108303	0	0	0
T143	0	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2546	0	0
T79	0	25	0	0
T105	736105	123	0	0
T125	0	249	0	0
T126	0	6	0	0
T127	0	2	0	0
T128	0	13	0	0
T129	0	7	0	0
T130	0	5	0	0
T131	0	214	0	0
T132	0	29	0	0
T133	986	0	0	0
T134	651270	0	0	0
T135	705941	0	0	0
T136	647871	0	0	0
T137	16771	0	0	0
T138	604368	0	0	0
T139	115142	0	0	0
T140	662531	0	0	0
T141	108303	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2561	0	0
T79	0	29	0	0
T105	736105	147	0	0
T125	0	208	0	0
T126	0	16	0	0
T127	0	9	0	0
T128	0	60	0	0
T129	0	12	0	0
T130	0	16	0	0
T131	0	249	0	0
T132	0	14	0	0
T133	986	0	0	0
T134	651270	0	0	0
T135	705941	0	0	0
T136	647871	0	0	0
T137	16771	0	0	0
T138	604368	0	0	0
T139	115142	0	0	0
T140	662531	0	0	0
T141	108303	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2696	0	0
T79	0	22	0	0
T105	736105	127	0	0
T125	0	243	0	0
T126	0	5	0	0
T127	0	8	0	0
T128	0	52	0	0
T129	0	15	0	0
T130	0	25	0	0
T131	0	272	0	0
T132	0	38	0	0
T133	986	0	0	0
T134	651270	0	0	0
T135	705941	0	0	0
T136	647871	0	0	0
T137	16771	0	0	0
T138	604368	0	0	0
T139	115142	0	0	0
T140	662531	0	0	0
T141	108303	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2634	0	0
T79	0	18	0	0
T105	736105	77	0	0
T125	0	262	0	0
T126	0	11	0	0
T127	0	8	0	0
T128	0	48	0	0
T129	0	20	0	0
T130	0	31	0	0
T131	0	242	0	0
T132	0	45	0	0
T133	986	0	0	0
T134	651270	0	0	0
T135	705941	0	0	0
T136	647871	0	0	0
T137	16771	0	0	0
T138	604368	0	0	0
T139	115142	0	0	0
T140	662531	0	0	0
T141	108303	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2564	0	0
T79	0	14	0	0
T105	736105	168	0	0
T125	0	224	0	0
T126	0	6	0	0
T127	0	5	0	0
T128	0	70	0	0
T129	0	17	0	0
T130	0	17	0	0
T131	0	257	0	0
T132	0	12	0	0
T133	986	0	0	0
T134	651270	0	0	0
T135	705941	0	0	0
T136	647871	0	0	0
T137	16771	0	0	0
T138	604368	0	0	0
T139	115142	0	0	0
T140	662531	0	0	0
T141	108303	0	0	0