Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.77	96.32	91.89	63.67	100.00	92.73	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	96.82	96.32	91.89	100.00	100.00	92.73	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.82	96.32	91.89	100.00	100.00	92.73	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.39	96.58	92.45	100.00	89.77	94.67	98.84

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
intr_fifo_empty	93.75	100.00	75.00			100.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	94.18	94.07	89.80		94.12	92.94	100.00
u_errchk	95.99	97.14	96.67		90.00	96.15	100.00
u_kmac_core	95.80	98.75	92.86	100.00	100.00	92.31	90.91
u_msgfifo	97.55	100.00	94.00		100.00	93.75	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.98	99.35	96.63	100.00		98.94	100.00
u_sha3	92.14	93.81	86.84	100.00	80.56	91.62	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.69	89.64	80.83			88.30	100.00
u_tlul_adapter_msgfifo	79.67	86.78	73.83			76.83	81.25

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		163	157	96.32
ALWAYS	343	0	0
ALWAYS	343	2	2	100.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	9	9	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	485	6	6	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	536	0	0
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	544	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
ALWAYS	560	5	5	100.00
CONT_ASSIGN	570	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	589	1	1	100.00
ALWAYS	609	3	3	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	632	1	1	100.00
CONT_ASSIGN	637	1	1	100.00
ALWAYS	640	7	5	71.43
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	681	1	0	0.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
ALWAYS	718	3	3	100.00
ALWAYS	722	28	28	100.00
CONT_ASSIGN	872	1	1	100.00
CONT_ASSIGN	875	1	1	100.00
CONT_ASSIGN	939	1	1	100.00
CONT_ASSIGN	941	1	1	100.00
CONT_ASSIGN	971	1	1	100.00
CONT_ASSIGN	976	1	1	100.00
CONT_ASSIGN	977	1	1	100.00
CONT_ASSIGN	979	1	1	100.00
CONT_ASSIGN	982	0	0
ALWAYS	1100	0	0
ALWAYS	1100	2	2	100.00
CONT_ASSIGN	1252	1	0	0.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1263	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1347	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
ALWAYS	1358	6	5	83.33
CONT_ASSIGN	1367	1	1	100.00
CONT_ASSIGN	1369	1	1	100.00
ALWAYS	1381	4	4	100.00
CONT_ASSIGN	1387	1	1	100.00
ALWAYS	1410	4	4	100.00
ALWAYS	1420	3	3	100.00
CONT_ASSIGN	1431	1	1	100.00
CONT_ASSIGN	1435	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	1	1
344	1	1
349	0	1
418	1	1
419	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
431	1	1
433	1	1
437	1	1
441	1	1
445	1	1
461	1	1
462	1	1
463	1	1
466	1	1
470	1	1
471	1	1
475	1	1
478	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
			MISSING_ELSE
510	1	1
515	1	1
522	1	1
525	1	1
526	1	1
527	1	1
530	5	5
531	5	5
534	1	1
536		unreachable
538	1	1
542	1	1
544	1	1
545	1	1
548	1	1
549	1	1
552	1	1
560	1	1
561	1	1
562	1	1
563	1	1
565	1	1
570	1	1
577	1	1
578	1	1
579	1	1
589	1	1
609	2	2
610	1	1
613	1	1
632	1	1
637	1	1
640	1	1
642	1	1
647	1	1
651	1	1
655	1	1
659	0	1
663	0	1
676	1	1
681	0	1
688	1	1
698	1	1
718	3	3
722	1	1
724	1	1
725	1	1
727	1	1
729	1	1
731	1	1
732	1	1
735	1	1
738	1	1
744	1	1
745	1	1
747	1	1
752	1	1
753	1	1
754	1	1
756	1	1
762	1	1
767	1	1
768	1	1
770	1	1
772	1	1
778	1	1
779	1	1
781	1	1
787	1	1
788	1	1
800	1	1
801	1	1
			MISSING_ELSE
872	1	1
875	1	1
939	1	1
941	1	1
971	1	1
976	1	1
977	1	1
979	1	1
982		unreachable
1100	1	1
1101	1	1
1252	0	1
1253	1	1
1254	1	1
1263	1	1
1269	1	1
1270	1	1
1271	1	1
1272	1	1
1275	1	1
1284	1	1
1326	1	1
1340	1	1
1347	1	1
1352	1	1
1358	1	1
1359	1	1
1360	1	1
1361	0	1
1362	1	1
1363	1	1
			MISSING_ELSE
1367	1	1
1369	1	1
1381	1	1
1382	1	1
1383	1	1
1384	1	1
			MISSING_ELSE
1387	1	1
1410	1	1
1411	1	1
1412	1	1
1414	1	1
			MISSING_ELSE
1420	1	1
1421	1	1
1424	1	1
1431	1	1
1435	1	1
1437	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	74	68	91.89
Logical	74	68	91.89
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T29,T30

 LINE       538
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T27

 LINE       542
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T51,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       549
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       562
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       562
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       562
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       570
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       613
 EXPRESSION (((~msgfifo_empty_q)) & msgfifo_empty)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       632
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T3,T15,T17
0	0	1	0	Not Covered
0	1	0	0	Covered	T3,T15,T20
1	0	0	0	Covered	T25,T26,T27

 LINE       676
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T4,T10,T11
0	1	0	0	Unreachable
1	0	0	0	Covered	T4,T10,T11

 LINE       688
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T4,T10,T11
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T4,T10,T11
0	0	1	0	0	0	Covered	T4,T10,T11
0	1	0	0	0	0	Covered	T4,T10,T11
1	0	0	0	0	0	Covered	T4,T10,T11

 LINE       729
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       731
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       745
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T2,T17,T25
1	Covered	T1,T2,T3

 LINE       971
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1101
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1340
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T19,T52,T53

 LINE       1340
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T19,T52,T53

 LINE       1369
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T4,T10,T11
0	0	1	0	0	Covered	T4,T5,T6
0	1	0	0	0	Covered	T4,T10,T11
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	64	90.14
Total Bits	6534	4160	63.67
Total Bits 0->1	3267	2080	63.67
Total Bits 1->0	3267	2080	63.67

Ports	71	64	90.14
Port Bits	6534	4160	63.67
Port Bits 0->1	3267	2080	63.67
Port Bits 1->0	3267	2080	63.67

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T25	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T4,T5,T25	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T4,T5,T25	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T20	Yes	T1,T2,T20	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T25,T26,T40	Yes	T25,T26,T40	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T19,T52,T53	Yes	T19,T52,T53	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T19,T4,T5	Yes	T19,T4,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T19,T52,T53	Yes	T19,T52,T53	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T19,T4,T5	Yes	T19,T4,T5	OUTPUT
keymgr_key_i.key[0][6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][8:7]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][13:9]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][15:14]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][35:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][36]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][39:37]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][40]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][79:41]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][80]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][101:81]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][103:102]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][108:104]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][109]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][137:110]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][138]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][140:139]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][141]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][159:142]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][160]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][171:161]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][172]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][176:173]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][178:177]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][194:179]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][196:195]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][229:197]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][230]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][231]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][232]	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	INPUT
keymgr_key_i.key[0][241:233]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][242]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][255:243]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][22:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][23]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][28:24]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][29]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][30]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][31]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][35:32]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][36]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][42:37]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][43]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][44]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][45]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][52:46]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][54:53]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][68:55]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][69]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][76:70]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][77]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][85:78]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][86]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][91:87]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][92]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][104:93]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][105]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][117:106]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][118]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][131:119]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][132]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][133]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][148:134]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][149]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][153:150]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][154]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][180:155]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][181]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][183:182]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][185:184]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][186]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][187]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][196:188]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][197]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][209:198]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][210]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][211]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][212]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][244:213]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][245]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][246]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][247]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][252:248]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][253]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][255:254]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
app_i[0].last	Yes	Yes	T2,T4,T25	Yes	T2,T15,T4	INPUT
app_i[0].strb[7:0]	Yes	Yes	T25,T29,T30	Yes	T25,T29,T30	INPUT
app_i[0].data[63:0]	Yes	Yes	T2,T15,T20	Yes	T2,T15,T20	INPUT
app_i[0].valid	Yes	Yes	T2,T15,T20	Yes	T2,T15,T20	INPUT
app_i[1].last	Yes	Yes	T2,T17,T4	Yes	T2,T17,T4	INPUT
app_i[1].strb[7:0]	Yes	Yes	T25,T29,T30	Yes	T25,T29,T30	INPUT
app_i[1].data[63:0]	Yes	Yes	T2,T17,T4	Yes	T2,T17,T4	INPUT
app_i[1].valid	Yes	Yes	T2,T17,T4	Yes	T2,T17,T4	INPUT
app_i[2].last	Yes	Yes	T2,T4,T25	Yes	T2,T4,T25	INPUT
app_i[2].strb[7:0]	Yes	Yes	T25,T29,T30	Yes	T25,T29,T30	INPUT
app_i[2].data[63:0]	Yes	Yes	T2,T4,T25	Yes	T2,T4,T25	INPUT
app_i[2].valid	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
app_o[0].error	Yes	Yes	T4,T5,T25	Yes	T4,T5,T25	OUTPUT
app_o[0].digest_share1[383:0]	No	No		No		OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T2,T25,T29	Yes	T2,T25,T29	OUTPUT
app_o[0].done	Yes	Yes	T2,T15,T25	Yes	T2,T15,T25	OUTPUT
app_o[0].ready	Yes	Yes	T2,T15,T20	Yes	T2,T15,T20	OUTPUT
app_o[1].error	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
app_o[1].digest_share1[383:0]	No	No		No		OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T2,T17,T29	Yes	T2,T17,T29	OUTPUT
app_o[1].done	Yes	Yes	T2,T17,T25	Yes	T2,T17,T25	OUTPUT
app_o[1].ready	Yes	Yes	T2,T17,T25	Yes	T2,T17,T25	OUTPUT
app_o[2].error	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
app_o[2].digest_share1[383:0]	No	No		No		OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T25,T29,T37	Yes	T25,T29,T37	OUTPUT
app_o[2].done	Yes	Yes	T2,T25,T29	Yes	T2,T25,T29	OUTPUT
app_o[2].ready	Yes	Yes	T2,T25,T29	Yes	T2,T25,T29	OUTPUT
entropy_o.edn_req	No	No		No		OUTPUT
entropy_i.edn_bus[31:0]	No	No		No		INPUT
entropy_i.edn_fips	No	No		No		INPUT
entropy_i.edn_ack	No	No		No		INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T5,T6,T33	Yes	T5,T6,T33	INPUT
intr_kmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_kmac_err_o	Yes	Yes	T3,T15,T20	Yes	T3,T15,T20	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	770	Covered	T1,T2,T3
KmacIdle	738	Covered	T1,T2,T3
KmacKeyBlock	745	Covered	T1,T2,T3
KmacMsgFeed	735	Covered	T1,T2,T3
KmacPrefix	732	Covered	T1,T2,T3
KmacTerminalError	787	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	779	Covered	T1,T2,T3
KmacDigest->KmacTerminalError	801	Covered	T38
KmacIdle->KmacMsgFeed	735	Covered	T1,T2,T3
KmacIdle->KmacPrefix	732	Covered	T1,T2,T3
KmacIdle->KmacTerminalError	801	Covered	T4,T10,T11
KmacKeyBlock->KmacMsgFeed	754	Covered	T1,T2,T3
KmacKeyBlock->KmacTerminalError	801	Covered	T7,T54,T55
KmacMsgFeed->KmacDigest	770	Covered	T1,T2,T3
KmacMsgFeed->KmacIdle	767	Covered	T2,T15,T17
KmacMsgFeed->KmacTerminalError	801	Covered	T6,T9,T33
KmacPrefix->KmacKeyBlock	745	Covered	T1,T2,T3
KmacPrefix->KmacMsgFeed	745	Covered	T2,T17,T25
KmacPrefix->KmacTerminalError	801	Covered	T5,T34,T56

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		55	51	92.73
TERNARY	423	2	2	100.00
CASE	431	6	5	83.33
IF	485	3	3	100.00
IF	560	3	3	100.00
IF	609	2	2	100.00
CASE	642	6	4	66.67
IF	718	2	2	100.00
CASE	727	15	15	100.00
IF	800	2	2	100.00
TERNARY	1101	2	2	100.00
IF	1358	4	3	75.00
IF	1381	3	3	100.00
IF	1410	3	3	100.00
IF	1420	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T3
CmdManualRun	Covered	T1,T2,T3
CmdDone	Covered	T1,T2,T3
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	560	if ((!rst_ni))
-2-:	562	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	609	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	642	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T3,T15,T20
errchecker_err.valid	Covered	T3,T15,T17
sha3_err.valid	Covered	T25,T26,T27
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	718	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	727	case (kmac_st)
-2-:	729	if ((kmac_cmd == CmdStart))
-3-:	731	if ((CShake == app_sha3_mode))
-4-:	744	if (sha3_block_processed)
-5-:	745	(app_kmac_en) ? 
-6-:	753	if (sha3_block_processed)
-7-:	762	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	768	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	778	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T2,T17,T25
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T1,T2,T3
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T2,T15,T17
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	Covered	T4,T10,T11

	LineNo.	Expression
-1-:	800	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1101	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1358	if ((!rst_ni))
-2-:	1360	if (alert_recov_operation)
-3-:	1362	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T20,T21,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1381	if ((!rst_ni))
-2-:	1383	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1410	if ((!rst_ni))
-2-:	1412	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1420	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1279394	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	337963	0	0
EntrySizeRegSameToEntrySizePkg_A	1037	1037	0	0
ErrProcessedLatched_A	2147483647	523	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	80	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	80	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	80	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacFsmCheck_A	2147483647	80	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	80	0	0
FpvSecCmRoundCountCheck_A	2147483647	80	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	80	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	80	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	80	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1037	1037	0	0
NumEntriesRegSameToNumEntriesPkg_A	1037	1037	0	0
PrefixRegSameToPrefixPkg_A	1037	1037	0	0
SecretKeyDivideBy32_A	1037	1037	0	0
Sha3AbsorbedPulse_A	2147483647	347697	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1279394	0	0
T1	111939	94	0	0
T2	235741	144	0	0
T3	864325	605	0	0
T12	144622	7936	0	0
T13	93753	295	0	0
T14	147894	7905	0	0
T15	798984	535	0	0
T16	322364	34	0	0
T17	0	282	0	0
T19	1439	0	0	0
T20	29487	1	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	337963	0	0
T1	111939	12	0	0
T2	235741	31	0	0
T3	864325	84	0	0
T12	144622	2202	0	0
T13	93753	41	0	0
T14	147894	2188	0	0
T15	798984	71	0	0
T16	322364	4	0	0
T17	0	38	0	0
T19	1439	0	0	0
T20	29487	6	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037	1037	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	523	0	0
T4	252235	0	0	0
T5	3117	0	0	0
T17	286053	0	0	0
T18	171724	0	0	0
T20	29487	6	0	0
T21	0	20	0	0
T22	0	14	0	0
T50	12917	0	0	0
T57	0	19	0	0
T58	0	17	0	0
T59	0	13	0	0
T60	0	4	0	0
T61	0	14	0	0
T62	0	10	0	0
T63	0	8	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037	1037	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037	1037	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037	1037	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037	1037	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347697	0	0
T1	111939	12	0	0
T2	235741	31	0	0
T3	864325	79	0	0
T12	144622	2265	0	0
T13	93753	41	0	0
T14	147894	2265	0	0
T15	798984	67	0	0
T16	322364	4	0	0
T17	0	38	0	0
T18	0	2337	0	0
T19	1439	0	0	0
T20	29487	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		163	157	96.32
ALWAYS	343	0	0
ALWAYS	343	2	2	100.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	9	9	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	485	6	6	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	536	0	0
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	544	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
ALWAYS	560	5	5	100.00
CONT_ASSIGN	570	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	589	1	1	100.00
ALWAYS	609	3	3	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	632	1	1	100.00
CONT_ASSIGN	637	1	1	100.00
ALWAYS	640	7	5	71.43
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	681	1	0	0.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
ALWAYS	718	3	3	100.00
ALWAYS	722	28	28	100.00
CONT_ASSIGN	872	1	1	100.00
CONT_ASSIGN	875	1	1	100.00
CONT_ASSIGN	939	1	1	100.00
CONT_ASSIGN	941	1	1	100.00
CONT_ASSIGN	971	1	1	100.00
CONT_ASSIGN	976	1	1	100.00
CONT_ASSIGN	977	1	1	100.00
CONT_ASSIGN	979	1	1	100.00
CONT_ASSIGN	982	0	0
ALWAYS	1100	0	0
ALWAYS	1100	2	2	100.00
CONT_ASSIGN	1252	1	0	0.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1263	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1347	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
ALWAYS	1358	6	5	83.33
CONT_ASSIGN	1367	1	1	100.00
CONT_ASSIGN	1369	1	1	100.00
ALWAYS	1381	4	4	100.00
CONT_ASSIGN	1387	1	1	100.00
ALWAYS	1410	4	4	100.00
ALWAYS	1420	3	3	100.00
CONT_ASSIGN	1431	1	1	100.00
CONT_ASSIGN	1435	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	1	1
344	1	1
349	0	1
418	1	1
419	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
431	1	1
433	1	1
437	1	1
441	1	1
445	1	1
461	1	1
462	1	1
463	1	1
466	1	1
470	1	1
471	1	1
475	1	1
478	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
			MISSING_ELSE
510	1	1
515	1	1
522	1	1
525	1	1
526	1	1
527	1	1
530	5	5
531	5	5
534	1	1
536		unreachable
538	1	1
542	1	1
544	1	1
545	1	1
548	1	1
549	1	1
552	1	1
560	1	1
561	1	1
562	1	1
563	1	1
565	1	1
570	1	1
577	1	1
578	1	1
579	1	1
589	1	1
609	2	2
610	1	1
613	1	1
632	1	1
637	1	1
640	1	1
642	1	1
647	1	1
651	1	1
655	1	1
659	0	1
663	0	1
676	1	1
681	0	1
688	1	1
698	1	1
718	3	3
722	1	1
724	1	1
725	1	1
727	1	1
729	1	1
731	1	1
732	1	1
735	1	1
738	1	1
744	1	1
745	1	1
747	1	1
752	1	1
753	1	1
754	1	1
756	1	1
762	1	1
767	1	1
768	1	1
770	1	1
772	1	1
778	1	1
779	1	1
781	1	1
787	1	1
788	1	1
800	1	1
801	1	1
			MISSING_ELSE
872	1	1
875	1	1
939	1	1
941	1	1
971	1	1
976	1	1
977	1	1
979	1	1
982		unreachable
1100	1	1
1101	1	1
1252	0	1
1253	1	1
1254	1	1
1263	1	1
1269	1	1
1270	1	1
1271	1	1
1272	1	1
1275	1	1
1284	1	1
1326	1	1
1340	1	1
1347	1	1
1352	1	1
1358	1	1
1359	1	1
1360	1	1
1361	0	1
1362	1	1
1363	1	1
			MISSING_ELSE
1367	1	1
1369	1	1
1381	1	1
1382	1	1
1383	1	1
1384	1	1
			MISSING_ELSE
1387	1	1
1410	1	1
1411	1	1
1412	1	1
1414	1	1
			MISSING_ELSE
1420	1	1
1421	1	1
1424	1	1
1431	1	1
1435	1	1
1437	6	6

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	74	68	91.89
Logical	74	68	91.89
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T29,T30

 LINE       538
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T27

 LINE       542
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T51,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       549
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       562
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       562
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       562
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       570
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       613
 EXPRESSION (((~msgfifo_empty_q)) & msgfifo_empty)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       632
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T3,T15,T17
0	0	1	0	Not Covered
0	1	0	0	Covered	T3,T15,T20
1	0	0	0	Covered	T25,T26,T27

 LINE       676
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T4,T10,T11
0	1	0	0	Unreachable
1	0	0	0	Covered	T4,T10,T11

 LINE       688
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T4,T10,T11
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T4,T10,T11
0	0	1	0	0	0	Covered	T4,T10,T11
0	1	0	0	0	0	Covered	T4,T10,T11
1	0	0	0	0	0	Covered	T4,T10,T11

 LINE       729
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       731
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       745
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T2,T17,T25
1	Covered	T1,T2,T3

 LINE       971
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1101
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1340
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T19,T52,T53

 LINE       1340
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T19,T52,T53

 LINE       1369
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T4,T10,T11
0	0	1	0	0	Covered	T4,T5,T6
0	1	0	0	0	Covered	T4,T10,T11
1	0	0	0	0	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	64	64	100.00
Total Bits	4160	4160	100.00
Total Bits 0->1	2080	2080	100.00
Total Bits 1->0	2080	2080	100.00

Ports	64	64	100.00
Port Bits	4160	4160	100.00
Port Bits 0->1	2080	2080	100.00
Port Bits 1->0	2080	2080	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T25	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T4,T5,T25	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T4,T5,T25	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T20	Yes	T1,T2,T20	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T25,T26,T40	Yes	T25,T26,T40	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T19,T52,T53	Yes	T19,T52,T53	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T19,T4,T5	Yes	T19,T4,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T19,T52,T53	Yes	T19,T52,T53	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T19,T4,T5	Yes	T19,T4,T5	OUTPUT
keymgr_key_i.key[0][6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][8:7]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][13:9]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][15:14]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][35:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][36]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][39:37]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][40]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][79:41]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][80]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][101:81]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][103:102]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][108:104]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][109]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][137:110]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][138]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][140:139]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][141]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][159:142]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][160]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][171:161]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][172]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][176:173]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][178:177]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][194:179]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][196:195]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][229:197]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][230]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][231]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][232]	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	INPUT
keymgr_key_i.key[0][241:233]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[0][242]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[0][255:243]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][22:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][23]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][28:24]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][29]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][30]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][31]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][35:32]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][36]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][42:37]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][43]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][44]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][45]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][52:46]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][54:53]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][68:55]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][69]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][76:70]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][77]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][85:78]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][86]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][91:87]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][92]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][104:93]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][105]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][117:106]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][118]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][131:119]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][132]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][133]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][148:134]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][149]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][153:150]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][154]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][180:155]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][181]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][183:182]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][185:184]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][186]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][187]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][196:188]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][197]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][209:198]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][210]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][211]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][212]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][244:213]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][245]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][246]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][247]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][252:248]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.key[1][253]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T13	INPUT
keymgr_key_i.key[1][255:254]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
keymgr_key_i.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
app_i[0].last	Yes	Yes	T2,T4,T25	Yes	T2,T15,T4	INPUT
app_i[0].strb[7:0]	Yes	Yes	T25,T29,T30	Yes	T25,T29,T30	INPUT
app_i[0].data[63:0]	Yes	Yes	T2,T15,T20	Yes	T2,T15,T20	INPUT
app_i[0].valid	Yes	Yes	T2,T15,T20	Yes	T2,T15,T20	INPUT
app_i[1].last	Yes	Yes	T2,T17,T4	Yes	T2,T17,T4	INPUT
app_i[1].strb[7:0]	Yes	Yes	T25,T29,T30	Yes	T25,T29,T30	INPUT
app_i[1].data[63:0]	Yes	Yes	T2,T17,T4	Yes	T2,T17,T4	INPUT
app_i[1].valid	Yes	Yes	T2,T17,T4	Yes	T2,T17,T4	INPUT
app_i[2].last	Yes	Yes	T2,T4,T25	Yes	T2,T4,T25	INPUT
app_i[2].strb[7:0]	Yes	Yes	T25,T29,T30	Yes	T25,T29,T30	INPUT
app_i[2].data[63:0]	Yes	Yes	T2,T4,T25	Yes	T2,T4,T25	INPUT
app_i[2].valid	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
app_o[0].error	Yes	Yes	T4,T5,T25	Yes	T4,T5,T25	OUTPUT
app_o[0].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[0].digest_share0[383:0]	Yes	Yes	T2,T25,T29	Yes	T2,T25,T29	OUTPUT
app_o[0].done	Yes	Yes	T2,T15,T25	Yes	T2,T15,T25	OUTPUT
app_o[0].ready	Yes	Yes	T2,T15,T20	Yes	T2,T15,T20	OUTPUT
app_o[1].error	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
app_o[1].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[1].digest_share0[383:0]	Yes	Yes	T2,T17,T29	Yes	T2,T17,T29	OUTPUT
app_o[1].done	Yes	Yes	T2,T17,T25	Yes	T2,T17,T25	OUTPUT
app_o[1].ready	Yes	Yes	T2,T17,T25	Yes	T2,T17,T25	OUTPUT
app_o[2].error	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
app_o[2].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[2].digest_share0[383:0]	Yes	Yes	T25,T29,T37	Yes	T25,T29,T37	OUTPUT
app_o[2].done	Yes	Yes	T2,T25,T29	Yes	T2,T25,T29	OUTPUT
app_o[2].ready	Yes	Yes	T2,T25,T29	Yes	T2,T25,T29	OUTPUT
entropy_o.edn_req[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_bus[31:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_fips[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_ack[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
lc_escalate_en_i[3:0]	Yes	Yes	T5,T6,T33	Yes	T5,T6,T33	INPUT
intr_kmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_kmac_err_o	Yes	Yes	T3,T15,T20	Yes	T3,T15,T20	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	770	Covered	T1,T2,T3
KmacIdle	738	Covered	T1,T2,T3
KmacKeyBlock	745	Covered	T1,T2,T3
KmacMsgFeed	735	Covered	T1,T2,T3
KmacPrefix	732	Covered	T1,T2,T3
KmacTerminalError	787	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	779	Covered	T1,T2,T3
KmacDigest->KmacTerminalError	801	Covered	T38
KmacIdle->KmacMsgFeed	735	Covered	T1,T2,T3
KmacIdle->KmacPrefix	732	Covered	T1,T2,T3
KmacIdle->KmacTerminalError	801	Covered	T4,T10,T11
KmacKeyBlock->KmacMsgFeed	754	Covered	T1,T2,T3
KmacKeyBlock->KmacTerminalError	801	Covered	T7,T54,T55
KmacMsgFeed->KmacDigest	770	Covered	T1,T2,T3
KmacMsgFeed->KmacIdle	767	Covered	T2,T15,T17
KmacMsgFeed->KmacTerminalError	801	Covered	T6,T9,T33
KmacPrefix->KmacKeyBlock	745	Covered	T1,T2,T3
KmacPrefix->KmacMsgFeed	745	Covered	T2,T17,T25
KmacPrefix->KmacTerminalError	801	Covered	T5,T34,T56

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		55	51	92.73
TERNARY	423	2	2	100.00
CASE	431	6	5	83.33
IF	485	3	3	100.00
IF	560	3	3	100.00
IF	609	2	2	100.00
CASE	642	6	4	66.67
IF	718	2	2	100.00
CASE	727	15	15	100.00
IF	800	2	2	100.00
TERNARY	1101	2	2	100.00
IF	1358	4	3	75.00
IF	1381	3	3	100.00
IF	1410	3	3	100.00
IF	1420	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T3
CmdManualRun	Covered	T1,T2,T3
CmdDone	Covered	T1,T2,T3
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	560	if ((!rst_ni))
-2-:	562	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	609	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	642	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T3,T15,T20
errchecker_err.valid	Covered	T3,T15,T17
sha3_err.valid	Covered	T25,T26,T27
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	718	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	727	case (kmac_st)
-2-:	729	if ((kmac_cmd == CmdStart))
-3-:	731	if ((CShake == app_sha3_mode))
-4-:	744	if (sha3_block_processed)
-5-:	745	(app_kmac_en) ? 
-6-:	753	if (sha3_block_processed)
-7-:	762	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	768	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	778	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T2,T17,T25
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T1,T2,T3
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T2,T15,T17
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	Covered	T4,T10,T11

	LineNo.	Expression
-1-:	800	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1101	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1358	if ((!rst_ni))
-2-:	1360	if (alert_recov_operation)
-3-:	1362	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T20,T21,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1381	if ((!rst_ni))
-2-:	1383	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1410	if ((!rst_ni))
-2-:	1412	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1420	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1279394	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	337963	0	0
EntrySizeRegSameToEntrySizePkg_A	1037	1037	0	0
ErrProcessedLatched_A	2147483647	523	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	80	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	80	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	80	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacFsmCheck_A	2147483647	80	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	80	0	0
FpvSecCmRoundCountCheck_A	2147483647	80	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	80	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	80	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	80	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1037	1037	0	0
NumEntriesRegSameToNumEntriesPkg_A	1037	1037	0	0
PrefixRegSameToPrefixPkg_A	1037	1037	0	0
SecretKeyDivideBy32_A	1037	1037	0	0
Sha3AbsorbedPulse_A	2147483647	347697	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1279394	0	0
T1	111939	94	0	0
T2	235741	144	0	0
T3	864325	605	0	0
T12	144622	7936	0	0
T13	93753	295	0	0
T14	147894	7905	0	0
T15	798984	535	0	0
T16	322364	34	0	0
T17	0	282	0	0
T19	1439	0	0	0
T20	29487	1	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	337963	0	0
T1	111939	12	0	0
T2	235741	31	0	0
T3	864325	84	0	0
T12	144622	2202	0	0
T13	93753	41	0	0
T14	147894	2188	0	0
T15	798984	71	0	0
T16	322364	4	0	0
T17	0	38	0	0
T19	1439	0	0	0
T20	29487	6	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037	1037	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	523	0	0
T4	252235	0	0	0
T5	3117	0	0	0
T17	286053	0	0	0
T18	171724	0	0	0
T20	29487	6	0	0
T21	0	20	0	0
T22	0	14	0	0
T50	12917	0	0	0
T57	0	19	0	0
T58	0	17	0	0
T59	0	13	0	0
T60	0	4	0	0
T61	0	14	0	0
T62	0	10	0	0
T63	0	8	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T4	252235	10	0	0
T5	3117	0	0	0
T10	0	10	0	0
T11	0	20	0	0
T25	127447	0	0	0
T29	494257	0	0	0
T50	12917	0	0	0
T64	18444	0	0	0
T65	135711	0	0	0
T66	626361	0	0	0
T67	17663	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	326300	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037	1037	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037	1037	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037	1037	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037	1037	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347697	0	0
T1	111939	12	0	0
T2	235741	31	0	0
T3	864325	79	0	0
T12	144622	2265	0	0
T13	93753	41	0	0
T14	147894	2265	0	0
T15	798984	67	0	0
T16	322364	4	0	0
T17	0	38	0	0
T18	0	2337	0	0
T19	1439	0	0	0
T20	29487	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	111939	111886	0	0
T2	235741	235684	0	0
T3	864325	864254	0	0
T12	144622	144621	0	0
T13	93753	93690	0	0
T14	147894	147894	0	0
T15	798984	798885	0	0
T16	322364	322277	0	0
T19	1439	1342	0	0
T20	29487	29428	0	0