Unified Coverage Report :: Module :: sha3

Module : sha3

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.45	97.30	81.25		81.82	91.89	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3	94.09	97.30	81.25		100.00	91.89	100.00

---

Module Instance : tb.dut.u_sha3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.09	97.30	81.25		100.00	91.89	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.80	91.76	86.84	100.00	80.56	91.62	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.80	96.15	91.89	100.00	100.00	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_keccak	81.47	81.77	88.24	100.00	40.00	78.79	100.00
u_pad	96.28	99.42	88.37	100.00	94.12	95.79	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : sha3

	Line No.	Total	Covered	Percent
TOTAL		74	72	97.30
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	176	6	6	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	189	1	1	100.00
ALWAYS	196	3	3	100.00
ALWAYS	206	38	38	100.00
ALWAYS	301	3	3	100.00
ALWAYS	318	12	10	83.33

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
132	1	1
138	1	1
142	1	1
160	1	1
167	2	2
168	1	1
172	1	1
176	2	2
177	2	2
178	1	1
179	1	1
			MISSING_ELSE
183	1	1
186	1	1
187	1	1
189	1	1
196	3	3
206	1	1
209	1	1
210	1	1
211	1	1
212	1	1
214	1	1
216	1	1
217	1	1
219	1	1
221	1	1
223	1	1
224	1	1
226	1	1
228	1	1
233	1	1
234	1	1
236	1	1
237	1	1
238	1	1
240	1	1
245	1	1
246	1	1
248	1	1
250	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
259	1	1
264	1	1
265	1	1
267	1	1
272	1	1
277	1	1
278	1	1
290	1	1
291	1	1
			MISSING_ELSE
301	1	1
302	1	1
303	1	1
318	1	1
320	1	1
322	1	1
324	1	1
			MISSING_ELSE
333	1	1
335	1	1
			MISSING_ELSE
344	1	1
345	0	1
			MISSING_ELSE
354	1	1
356	1	1
			MISSING_ELSE
365	1	1
367	0	1
			MISSING_ELSE

---

Cond Coverage for Module : sha3

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       132
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       138
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T10,T11,T12
0	1	0	Covered	T10,T11,T12
1	0	0	Covered	T10,T11,T12

 LINE       160
 EXPRESSION (sha3pad_keccak_run | sw_keccak_run)
             ---------1--------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T14,T15
1	0	Covered	T1,T2,T3

 LINE       233
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION (start_i || process_i)
             ---1---    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Module : sha3

Summary for FSM :: st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	11	9	81.82
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorb_sparse	224	Covered	T1,T2,T3
StFlush_sparse	255	Covered	T1,T2,T3
StIdle_sparse	228	Covered	T1,T2,T3
StManualRun_sparse	251	Covered	T3,T14,T15
StSqueeze_sparse	238	Covered	T1,T2,T3
StTerminalError_sparse	277	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
StAbsorb_sparse->StSqueeze_sparse	238	Covered	T1,T2,T3
StAbsorb_sparse->StTerminalError_sparse	291	Covered	T4,T5,T6
StFlush_sparse->StIdle_sparse	272	Covered	T1,T2,T3
StFlush_sparse->StTerminalError_sparse	291	Not Covered
StIdle_sparse->StAbsorb_sparse	224	Covered	T1,T2,T3
StIdle_sparse->StTerminalError_sparse	291	Covered	T10,T11,T12
StManualRun_sparse->StSqueeze_sparse	265	Covered	T3,T14,T15
StManualRun_sparse->StTerminalError_sparse	291	Not Covered
StSqueeze_sparse->StFlush_sparse	255	Covered	T1,T2,T3
StSqueeze_sparse->StManualRun_sparse	251	Covered	T3,T14,T15
StSqueeze_sparse->StTerminalError_sparse	291	Covered	T43,T44

---

Branch Coverage for Module : sha3

	Line No.	Total	Covered	Percent
Branches		37	34	91.89
IF	167	2	2	100.00
IF	176	4	4	100.00
IF	196	2	2	100.00
CASE	221	13	13	100.00
IF	290	2	2	100.00
CASE	301	3	2	66.67
CASE	320	11	9	81.82

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	176	if ((!rst_ni))
-2-:	177	if (process_i)
-3-:	178	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	196	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	221	case (st)
-2-:	223	if (start_i)
-3-:	233	if ((process_i && (!processing)))
-4-:	237	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))
-5-:	250	if (run_i)
-6-:	254	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))
-7-:	264	if (keccak_complete)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle_sparse	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle_sparse	0	-	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	1	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	0	1	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	0	0	-	-	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	-	1	-	-	Covered	T3,T14,T15
StSqueeze_sparse	-	-	-	0	1	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	-	0	0	-	Covered	T1,T2,T3
StManualRun_sparse	-	-	-	-	-	1	Covered	T3,T14,T15
StManualRun_sparse	-	-	-	-	-	0	Covered	T3,T14,T15
StFlush_sparse	-	-	-	-	-	-	Covered	T1,T2,T3
StTerminalError_sparse	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	290	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	301	case (mux_sel)

Branches:

-1-	Status	Tests
MuxGuard	Covered	T1,T2,T3
MuxRelease	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	320	case (st)
-2-:	322	if (((process_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-3-:	333	if ((((start_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)) || (process_i && processing)))
-4-:	344	if ((start_i || process_i))
-5-:	354	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-6-:	365	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle_sparse	1	-	-	-	-	Covered	T27,T28,T29
StIdle_sparse	0	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	1	-	-	-	Covered	T27,T28,T29
StAbsorb_sparse	-	0	-	-	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	0	-	-	Covered	T1,T2,T3
StManualRun_sparse	-	-	-	1	-	Covered	T27,T28,T29
StManualRun_sparse	-	-	-	0	-	Covered	T3,T14,T15
StFlush_sparse	-	-	-	-	1	Not Covered
StFlush_sparse	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Covered	T4,T5,T6

---

Assert Coverage for Module : sha3

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrDetection_A	2147483647	8611623	0	0
FsmKnown_A	2147483647	2147483647	0	0
MuxSelKnown_A	2147483647	2147483647	0	0
SwRunInSqueezing_a	2147483647	158021	0	0
gen_chk_digest_unmasked.StateZeroInvalid_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ErrDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8611623	0	0
T6	2762	0	0	0
T27	998345	92971	0	0
T28	0	23691	0	0
T29	0	134889	0	0
T45	0	236325	0	0
T46	0	73090	0	0
T47	0	125910	0	0
T48	0	306532	0	0
T49	0	155621	0	0
T50	0	67504	0	0
T51	0	275375	0	0
T52	970320	0	0	0
T53	323950	0	0	0
T54	504379	0	0	0
T55	486843	0	0	0
T56	91361	0	0	0
T57	49349	0	0	0
T58	646957	0	0	0
T59	172657	0	0	0

FsmKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

MuxSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

SwRunInSqueezing_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	158021	0	0
T3	210024	640	0	0
T13	328668	0	0	0
T14	488585	130	0	0
T15	169062	424	0	0
T16	219586	0	0	0
T17	16603	0	0	0
T18	70573	0	0	0
T19	232987	542	0	0
T23	0	467	0	0
T38	178349	0	0	0
T39	445809	264	0	0
T40	0	251	0	0
T60	0	311	0	0
T61	0	586	0	0
T62	0	211	0	0

gen_chk_digest_unmasked.StateZeroInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	129135	0	0
T2	939753	889284	0	0
T3	210024	132208	0	0
T13	328668	315284	0	0
T14	488585	378601	0	0
T15	169062	132041	0	0
T16	219586	204215	0	0
T17	16603	11726	0	0
T18	70573	41509	0	0
T19	232987	219718	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

Line Coverage for Instance : tb.dut.u_sha3

	Line No.	Total	Covered	Percent
TOTAL		74	72	97.30
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	176	6	6	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	189	1	1	100.00
ALWAYS	196	3	3	100.00
ALWAYS	206	38	38	100.00
ALWAYS	301	3	3	100.00
ALWAYS	318	12	10	83.33

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
132	1	1
138	1	1
142	1	1
160	1	1
167	2	2
168	1	1
172	1	1
176	2	2
177	2	2
178	1	1
179	1	1
			MISSING_ELSE
183	1	1
186	1	1
187	1	1
189	1	1
196	3	3
206	1	1
209	1	1
210	1	1
211	1	1
212	1	1
214	1	1
216	1	1
217	1	1
219	1	1
221	1	1
223	1	1
224	1	1
226	1	1
228	1	1
233	1	1
234	1	1
236	1	1
237	1	1
238	1	1
240	1	1
245	1	1
246	1	1
248	1	1
250	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
259	1	1
264	1	1
265	1	1
267	1	1
272	1	1
277	1	1
278	1	1
290	1	1
291	1	1
			MISSING_ELSE
301	1	1
302	1	1
303	1	1
318	1	1
320	1	1
322	1	1
324	1	1
			MISSING_ELSE
333	1	1
335	1	1
			MISSING_ELSE
344	1	1
345	0	1
			MISSING_ELSE
354	1	1
356	1	1
			MISSING_ELSE
365	1	1
367	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       132
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       138
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T10,T11,T12
0	1	0	Covered	T10,T11,T12
1	0	0	Covered	T10,T11,T12

 LINE       160
 EXPRESSION (sha3pad_keccak_run | sw_keccak_run)
             ---------1--------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T14,T15
1	0	Covered	T1,T2,T3

 LINE       233
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION (start_i || process_i)
             ---1---    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Instance : tb.dut.u_sha3

Summary for FSM :: st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	9	9	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorb_sparse	224	Covered	T1,T2,T3
StFlush_sparse	255	Covered	T1,T2,T3
StIdle_sparse	228	Covered	T1,T2,T3
StManualRun_sparse	251	Covered	T3,T14,T15
StSqueeze_sparse	238	Covered	T1,T2,T3
StTerminalError_sparse	277	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
StAbsorb_sparse->StSqueeze_sparse	238	Covered	T1,T2,T3
StAbsorb_sparse->StTerminalError_sparse	291	Covered	T4,T5,T6
StFlush_sparse->StIdle_sparse	272	Covered	T1,T2,T3
StFlush_sparse->StTerminalError_sparse	291	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StIdle_sparse->StAbsorb_sparse	224	Covered	T1,T2,T3
StIdle_sparse->StTerminalError_sparse	291	Covered	T10,T11,T12
StManualRun_sparse->StSqueeze_sparse	265	Covered	T3,T14,T15
StManualRun_sparse->StTerminalError_sparse	291	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StSqueeze_sparse->StFlush_sparse	255	Covered	T1,T2,T3
StSqueeze_sparse->StManualRun_sparse	251	Covered	T3,T14,T15
StSqueeze_sparse->StTerminalError_sparse	291	Covered	T43,T44

---

Branch Coverage for Instance : tb.dut.u_sha3

	Line No.	Total	Covered	Percent
Branches		37	34	91.89
IF	167	2	2	100.00
IF	176	4	4	100.00
IF	196	2	2	100.00
CASE	221	13	13	100.00
IF	290	2	2	100.00
CASE	301	3	2	66.67
CASE	320	11	9	81.82

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	176	if ((!rst_ni))
-2-:	177	if (process_i)
-3-:	178	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	196	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	221	case (st)
-2-:	223	if (start_i)
-3-:	233	if ((process_i && (!processing)))
-4-:	237	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))
-5-:	250	if (run_i)
-6-:	254	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))
-7-:	264	if (keccak_complete)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle_sparse	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle_sparse	0	-	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	1	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	0	1	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	0	0	-	-	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	-	1	-	-	Covered	T3,T14,T15
StSqueeze_sparse	-	-	-	0	1	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	-	0	0	-	Covered	T1,T2,T3
StManualRun_sparse	-	-	-	-	-	1	Covered	T3,T14,T15
StManualRun_sparse	-	-	-	-	-	0	Covered	T3,T14,T15
StFlush_sparse	-	-	-	-	-	-	Covered	T1,T2,T3
StTerminalError_sparse	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	290	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	301	case (mux_sel)

Branches:

-1-	Status	Tests
MuxGuard	Covered	T1,T2,T3
MuxRelease	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	320	case (st)
-2-:	322	if (((process_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-3-:	333	if ((((start_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)) || (process_i && processing)))
-4-:	344	if ((start_i || process_i))
-5-:	354	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-6-:	365	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle_sparse	1	-	-	-	-	Covered	T27,T28,T29
StIdle_sparse	0	-	-	-	-	Covered	T1,T2,T3
StAbsorb_sparse	-	1	-	-	-	Covered	T27,T28,T29
StAbsorb_sparse	-	0	-	-	-	Covered	T1,T2,T3
StSqueeze_sparse	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	0	-	-	Covered	T1,T2,T3
StManualRun_sparse	-	-	-	1	-	Covered	T27,T28,T29
StManualRun_sparse	-	-	-	0	-	Covered	T3,T14,T15
StFlush_sparse	-	-	-	-	1	Not Covered
StFlush_sparse	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sha3

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrDetection_A	2147483647	8611623	0	0
FsmKnown_A	2147483647	2147483647	0	0
MuxSelKnown_A	2147483647	2147483647	0	0
SwRunInSqueezing_a	2147483647	158021	0	0
gen_chk_digest_unmasked.StateZeroInvalid_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ErrDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8611623	0	0
T6	2762	0	0	0
T27	998345	92971	0	0
T28	0	23691	0	0
T29	0	134889	0	0
T45	0	236325	0	0
T46	0	73090	0	0
T47	0	125910	0	0
T48	0	306532	0	0
T49	0	155621	0	0
T50	0	67504	0	0
T51	0	275375	0	0
T52	970320	0	0	0
T53	323950	0	0	0
T54	504379	0	0	0
T55	486843	0	0	0
T56	91361	0	0	0
T57	49349	0	0	0
T58	646957	0	0	0
T59	172657	0	0	0

FsmKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

MuxSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

SwRunInSqueezing_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	158021	0	0
T3	210024	640	0	0
T13	328668	0	0	0
T14	488585	130	0	0
T15	169062	424	0	0
T16	219586	0	0	0
T17	16603	0	0	0
T18	70573	0	0	0
T19	232987	542	0	0
T23	0	467	0	0
T38	178349	0	0	0
T39	445809	264	0	0
T40	0	251	0	0
T60	0	311	0	0
T61	0	586	0	0
T62	0	211	0	0

gen_chk_digest_unmasked.StateZeroInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	129135	0	0
T2	939753	889284	0	0
T3	210024	132208	0	0
T13	328668	315284	0	0
T14	488585	378601	0	0
T15	169062	132041	0	0
T16	219586	204215	0	0
T17	16603	11726	0	0
T18	70573	41509	0	0
T19	232987	219718	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0