Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.74	96.15	91.89	63.67	100.00	92.73	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	96.80	96.15	91.89	100.00	100.00	92.73	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.80	96.15	91.89	100.00	100.00	92.73	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.93	96.25	92.34	100.00	87.50	94.66	98.84

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
intr_fifo_empty	93.75	100.00	75.00			100.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	93.01	94.07	89.80		88.24	92.94	100.00
u_errchk	95.99	97.14	96.67		90.00	96.15	100.00
u_kmac_core	93.72	98.75	92.86	100.00	87.50	92.31	90.91
u_msgfifo	97.55	100.00	94.00		100.00	93.75	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.96	99.33	96.55	100.00		98.93	100.00
u_sha3	91.80	91.76	86.84	100.00	80.56	91.62	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.69	89.64	80.83			88.30	100.00
u_tlul_adapter_msgfifo	79.67	86.78	73.83			76.83	81.25

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		156	150	96.15
ALWAYS	343	0	0
ALWAYS	343	2	2	100.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	9	9	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	485	6	6	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	534	0	0
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
ALWAYS	558	5	5	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
ALWAYS	607	3	3	100.00
CONT_ASSIGN	611	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
ALWAYS	638	7	5	71.43
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	679	1	0	0.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	696	1	1	100.00
ALWAYS	716	3	3	100.00
ALWAYS	720	28	28	100.00
CONT_ASSIGN	870	1	1	100.00
CONT_ASSIGN	873	1	1	100.00
CONT_ASSIGN	938	1	1	100.00
CONT_ASSIGN	940	1	1	100.00
CONT_ASSIGN	970	1	1	100.00
CONT_ASSIGN	975	1	1	100.00
CONT_ASSIGN	976	1	1	100.00
CONT_ASSIGN	978	1	1	100.00
CONT_ASSIGN	981	0	0
ALWAYS	1099	0	0
ALWAYS	1099	2	2	100.00
CONT_ASSIGN	1252	1	0	0.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1264	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1328	1	1	100.00
CONT_ASSIGN	1342	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1354	1	1	100.00
ALWAYS	1360	6	5	83.33
CONT_ASSIGN	1369	1	1	100.00
CONT_ASSIGN	1371	1	1	100.00
ALWAYS	1383	4	4	100.00
CONT_ASSIGN	1389	1	1	100.00
ALWAYS	1412	4	4	100.00
ALWAYS	1422	3	3	100.00
CONT_ASSIGN	1433	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	1	1
344	1	1
349	0	1
418	1	1
419	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
431	1	1
433	1	1
437	1	1
441	1	1
445	1	1
461	1	1
462	1	1
463	1	1
466	1	1
470	1	1
471	1	1
475	1	1
478	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
			MISSING_ELSE
510	1	1
515	1	1
522	1	1
525	1	1
526	1	1
527	1	1
529	1	1
530	1	1
532	1	1
534		unreachable
536	1	1
540	1	1
542	1	1
543	1	1
546	1	1
547	1	1
550	1	1
558	1	1
559	1	1
560	1	1
561	1	1
563	1	1
568	1	1
575	1	1
576	1	1
577	1	1
587	1	1
607	2	2
608	1	1
611	1	1
630	1	1
635	1	1
638	1	1
640	1	1
645	1	1
649	1	1
653	1	1
657	0	1
661	0	1
674	1	1
679	0	1
686	1	1
696	1	1
716	3	3
720	1	1
722	1	1
723	1	1
725	1	1
727	1	1
729	1	1
730	1	1
733	1	1
736	1	1
742	1	1
743	1	1
745	1	1
750	1	1
751	1	1
752	1	1
754	1	1
760	1	1
765	1	1
766	1	1
768	1	1
770	1	1
776	1	1
777	1	1
779	1	1
785	1	1
786	1	1
798	1	1
799	1	1
			MISSING_ELSE
870	1	1
873	1	1
938	1	1
940	1	1
970	1	1
975	1	1
976	1	1
978	1	1
981		unreachable
1099	1	1
1100	1	1
1252	0	1
1253	1	1
1254	1	1
1264	1	1
1265	1	1
1271	1	1
1272	1	1
1273	1	1
1274	1	1
1277	1	1
1286	1	1
1328	1	1
1342	1	1
1349	1	1
1354	1	1
1360	1	1
1361	1	1
1362	1	1
1363	0	1
1364	1	1
1365	1	1
			MISSING_ELSE
1369	1	1
1371	1	1
1383	1	1
1384	1	1
1385	1	1
1386	1	1
			MISSING_ELSE
1389	1	1
1412	1	1
1413	1	1
1414	1	1
1416	1	1
			MISSING_ELSE
1422	1	1
1423	1	1
1426	1	1
1433	1	1
1437	1	1
1439	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	74	68	91.89
Logical	74	68	91.89
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T14,T27,T10

 LINE       536
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T14,T15,T27

 LINE       540
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       547
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       568
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       611
 EXPRESSION (((~msgfifo_empty_q)) & msgfifo_empty)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       630
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T32,T33,T63
0	0	1	0	Not Covered
0	1	0	0	Covered	T20,T4,T5
1	0	0	0	Covered	T27,T28,T29

 LINE       674
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T10,T11,T12
0	1	0	0	Unreachable
1	0	0	0	Covered	T10,T11,T12

 LINE       686
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T10,T11,T12
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T10,T11,T12
0	0	1	0	0	0	Covered	T10,T11,T12
0	1	0	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	0	Covered	T10,T11,T12

 LINE       727
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       729
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T14,T15

 LINE       743
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T14,T15,T23
1	Covered	T3,T14,T15

 LINE       970
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1100
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1342
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T64,T65
1	0	Covered	T1,T2,T3
1	1	Covered	T41,T64,T65

 LINE       1342
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T64,T65
1	0	Covered	T1,T2,T3
1	1	Covered	T41,T64,T65

 LINE       1371
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T10,T11,T12
0	0	1	0	0	Covered	T4,T5,T6
0	1	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	64	90.14
Total Bits	6534	4160	63.67
Total Bits 0->1	3267	2080	63.67
Total Bits 1->0	3267	2080	63.67

Ports	71	64	90.14
Port Bits	6534	4160	63.67
Port Bits 0->1	3267	2080	63.67
Port Bits 1->0	3267	2080	63.67

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T15,T4,T5	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T15,T4,T5	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T15,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T13,T14	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T13,T15,T16	Yes	T13,T15,T16	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T28,T66,T67	Yes	T28,T66,T67	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T41,T64,T4	Yes	T41,T64,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T41,T64,T4	Yes	T41,T64,T4	OUTPUT
keymgr_key_i.key[1:0][255:0]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
keymgr_key_i.valid	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
app_i[0].last	Yes	Yes	T14,T15,T23	Yes	T14,T15,T23	INPUT
app_i[0].strb[7:0]	Yes	Yes	T14,T15,T27	Yes	T14,T15,T27	INPUT
app_i[0].data[63:0]	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
app_i[0].valid	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
app_i[1].last	Yes	Yes	T14,T23,T32	Yes	T14,T15,T23	INPUT
app_i[1].strb[7:0]	Yes	Yes	T14,T15,T27	Yes	T14,T15,T27	INPUT
app_i[1].data[63:0]	Yes	Yes	T14,T15,T23	Yes	T14,T15,T23	INPUT
app_i[1].valid	Yes	Yes	T14,T15,T4	Yes	T14,T15,T4	INPUT
app_i[2].last	Yes	Yes	T23,T32,T27	Yes	T15,T23,T32	INPUT
app_i[2].strb[7:0]	Yes	Yes	T15,T27,T30	Yes	T15,T27,T30	INPUT
app_i[2].data[63:0]	Yes	Yes	T15,T23,T32	Yes	T15,T23,T32	INPUT
app_i[2].valid	Yes	Yes	T15,T4,T23	Yes	T15,T4,T23	INPUT
app_o[0].error	Yes	Yes	T4,T5,T27	Yes	T4,T5,T27	OUTPUT
app_o[0].digest_share1[383:0]	No	No		No		OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T14,T15,T23	Yes	T14,T15,T23	OUTPUT
app_o[0].done	Yes	Yes	T14,T15,T23	Yes	T14,T15,T23	OUTPUT
app_o[0].ready	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	OUTPUT
app_o[1].error	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	OUTPUT
app_o[1].digest_share1[383:0]	No	No		No		OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T14,T15,T23	Yes	T14,T15,T23	OUTPUT
app_o[1].done	Yes	Yes	T14,T15,T23	Yes	T14,T15,T23	OUTPUT
app_o[1].ready	Yes	Yes	T14,T15,T23	Yes	T14,T15,T23	OUTPUT
app_o[2].error	Yes	Yes	T28,T29,T45	Yes	T28,T29,T45	OUTPUT
app_o[2].digest_share1[383:0]	No	No		No		OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T23,T27,T30	Yes	T23,T27,T30	OUTPUT
app_o[2].done	Yes	Yes	T15,T23,T32	Yes	T15,T23,T32	OUTPUT
app_o[2].ready	Yes	Yes	T15,T23,T32	Yes	T15,T23,T32	OUTPUT
entropy_o.edn_req	No	No		No		OUTPUT
entropy_i.edn_bus[31:0]	No	No		No		INPUT
entropy_i.edn_fips	No	No		No		INPUT
entropy_i.edn_ack	No	No		No		INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
intr_kmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_kmac_err_o	Yes	Yes	T20,T4,T5	Yes	T20,T4,T5	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	768	Covered	T1,T2,T3
KmacIdle	736	Covered	T1,T2,T3
KmacKeyBlock	743	Covered	T3,T14,T15
KmacMsgFeed	733	Covered	T1,T2,T3
KmacPrefix	730	Covered	T3,T14,T15
KmacTerminalError	785	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	777	Covered	T1,T2,T3
KmacDigest->KmacTerminalError	799	Covered	T43,T44
KmacIdle->KmacMsgFeed	733	Covered	T1,T2,T3
KmacIdle->KmacPrefix	730	Covered	T3,T14,T15
KmacIdle->KmacTerminalError	799	Covered	T10,T11,T12
KmacKeyBlock->KmacMsgFeed	752	Covered	T3,T14,T15
KmacKeyBlock->KmacTerminalError	799	Covered	T4,T5,T7
KmacMsgFeed->KmacDigest	768	Covered	T1,T2,T3
KmacMsgFeed->KmacIdle	765	Covered	T14,T15,T23
KmacMsgFeed->KmacTerminalError	799	Covered	T6,T9,T68
KmacPrefix->KmacKeyBlock	743	Covered	T3,T14,T15
KmacPrefix->KmacMsgFeed	743	Covered	T14,T15,T23
KmacPrefix->KmacTerminalError	799	Covered	T69,T8,T70

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		55	51	92.73
TERNARY	423	2	2	100.00
CASE	431	6	5	83.33
IF	485	3	3	100.00
IF	558	3	3	100.00
IF	607	2	2	100.00
CASE	640	6	4	66.67
IF	716	2	2	100.00
CASE	725	15	15	100.00
IF	798	2	2	100.00
TERNARY	1100	2	2	100.00
IF	1360	4	3	75.00
IF	1383	3	3	100.00
IF	1412	3	3	100.00
IF	1422	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T3
CmdManualRun	Covered	T3,T14,T15
CmdDone	Covered	T1,T2,T3
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	if ((!rst_ni))
-2-:	560	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	607	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	640	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T20,T4,T5
errchecker_err.valid	Covered	T32,T33,T63
sha3_err.valid	Covered	T27,T28,T29
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	716	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	725	case (kmac_st)
-2-:	727	if ((kmac_cmd == CmdStart))
-3-:	729	if ((CShake == app_sha3_mode))
-4-:	742	if (sha3_block_processed)
-5-:	743	(app_kmac_en) ? 
-6-:	751	if (sha3_block_processed)
-7-:	760	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	766	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	776	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T3,T14,T15
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T3,T14,T15
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T14,T15,T23
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T3,T14,T15
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T3,T14,T15
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T3,T14,T15
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T14,T15,T23
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	798	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1100	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1360	if ((!rst_ni))
-2-:	1362	if (alert_recov_operation)
-3-:	1364	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T20,T21,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1383	if ((!rst_ni))
-2-:	1385	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1412	if ((!rst_ni))
-2-:	1414	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1422	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1298277	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	341393	0	0
EntrySizeRegSameToEntrySizePkg_A	1030	1030	0	0
ErrProcessedLatched_A	2147483647	572	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	80	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	80	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	80	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacFsmCheck_A	2147483647	80	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	80	0	0
FpvSecCmRoundCountCheck_A	2147483647	80	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	80	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	80	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	80	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1030	1030	0	0
NumEntriesRegSameToNumEntriesPkg_A	1030	1030	0	0
PrefixRegSameToPrefixPkg_A	1030	1030	0	0
SecretKeyDivideBy32_A	1030	1030	0	0
Sha3AbsorbedPulse_A	2147483647	351441	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1298277	0	0
T1	135261	983	0	0
T2	939753	786	0	0
T3	210024	1391	0	0
T13	328668	786	0	0
T14	488585	325	0	0
T15	169062	1043	0	0
T16	219586	7511	0	0
T17	16603	28	0	0
T18	70573	457	0	0
T19	232987	1166	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	341393	0	0
T1	135261	298	0	0
T2	939753	240	0	0
T3	210024	198	0	0
T13	328668	238	0	0
T14	488585	65	0	0
T15	169062	170	0	0
T16	219586	2269	0	0
T17	16603	9	0	0
T18	70573	140	0	0
T19	232987	162	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	572	0	0
T4	3317	0	0	0
T5	2853	0	0	0
T20	124123	20	0	0
T21	0	20	0	0
T22	0	8	0	0
T23	467564	0	0	0
T24	0	8	0	0
T61	371701	0	0	0
T62	127978	0	0	0
T65	1738	0	0	0
T71	0	3	0	0
T72	0	9	0	0
T73	0	2	0	0
T74	0	9	0	0
T75	0	14	0	0
T76	0	5	0	0
T77	122646	0	0	0
T78	16578	0	0	0
T79	123561	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	351441	0	0
T1	135261	310	0	0
T2	939753	246	0	0
T3	210024	199	0	0
T13	328668	246	0	0
T14	488585	65	0	0
T15	169062	173	0	0
T16	219586	2337	0	0
T17	16603	9	0	0
T18	70573	142	0	0
T19	232987	162	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		156	150	96.15
ALWAYS	343	0	0
ALWAYS	343	2	2	100.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	9	9	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	485	6	6	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	534	0	0
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
ALWAYS	558	5	5	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
ALWAYS	607	3	3	100.00
CONT_ASSIGN	611	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
ALWAYS	638	7	5	71.43
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	679	1	0	0.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	696	1	1	100.00
ALWAYS	716	3	3	100.00
ALWAYS	720	28	28	100.00
CONT_ASSIGN	870	1	1	100.00
CONT_ASSIGN	873	1	1	100.00
CONT_ASSIGN	938	1	1	100.00
CONT_ASSIGN	940	1	1	100.00
CONT_ASSIGN	970	1	1	100.00
CONT_ASSIGN	975	1	1	100.00
CONT_ASSIGN	976	1	1	100.00
CONT_ASSIGN	978	1	1	100.00
CONT_ASSIGN	981	0	0
ALWAYS	1099	0	0
ALWAYS	1099	2	2	100.00
CONT_ASSIGN	1252	1	0	0.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1264	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1328	1	1	100.00
CONT_ASSIGN	1342	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1354	1	1	100.00
ALWAYS	1360	6	5	83.33
CONT_ASSIGN	1369	1	1	100.00
CONT_ASSIGN	1371	1	1	100.00
ALWAYS	1383	4	4	100.00
CONT_ASSIGN	1389	1	1	100.00
ALWAYS	1412	4	4	100.00
ALWAYS	1422	3	3	100.00
CONT_ASSIGN	1433	1	1	100.00
CONT_ASSIGN	1437	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	1	1
344	1	1
349	0	1
418	1	1
419	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
431	1	1
433	1	1
437	1	1
441	1	1
445	1	1
461	1	1
462	1	1
463	1	1
466	1	1
470	1	1
471	1	1
475	1	1
478	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
			MISSING_ELSE
510	1	1
515	1	1
522	1	1
525	1	1
526	1	1
527	1	1
529	1	1
530	1	1
532	1	1
534		unreachable
536	1	1
540	1	1
542	1	1
543	1	1
546	1	1
547	1	1
550	1	1
558	1	1
559	1	1
560	1	1
561	1	1
563	1	1
568	1	1
575	1	1
576	1	1
577	1	1
587	1	1
607	2	2
608	1	1
611	1	1
630	1	1
635	1	1
638	1	1
640	1	1
645	1	1
649	1	1
653	1	1
657	0	1
661	0	1
674	1	1
679	0	1
686	1	1
696	1	1
716	3	3
720	1	1
722	1	1
723	1	1
725	1	1
727	1	1
729	1	1
730	1	1
733	1	1
736	1	1
742	1	1
743	1	1
745	1	1
750	1	1
751	1	1
752	1	1
754	1	1
760	1	1
765	1	1
766	1	1
768	1	1
770	1	1
776	1	1
777	1	1
779	1	1
785	1	1
786	1	1
798	1	1
799	1	1
			MISSING_ELSE
870	1	1
873	1	1
938	1	1
940	1	1
970	1	1
975	1	1
976	1	1
978	1	1
981		unreachable
1099	1	1
1100	1	1
1252	0	1
1253	1	1
1254	1	1
1264	1	1
1265	1	1
1271	1	1
1272	1	1
1273	1	1
1274	1	1
1277	1	1
1286	1	1
1328	1	1
1342	1	1
1349	1	1
1354	1	1
1360	1	1
1361	1	1
1362	1	1
1363	0	1
1364	1	1
1365	1	1
			MISSING_ELSE
1369	1	1
1371	1	1
1383	1	1
1384	1	1
1385	1	1
1386	1	1
			MISSING_ELSE
1389	1	1
1412	1	1
1413	1	1
1414	1	1
1416	1	1
			MISSING_ELSE
1422	1	1
1423	1	1
1426	1	1
1433	1	1
1437	1	1
1439	6	6

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	74	68	91.89
Logical	74	68	91.89
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T14,T27,T10

 LINE       536
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T14,T15,T27

 LINE       540
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       547
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       568
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       611
 EXPRESSION (((~msgfifo_empty_q)) & msgfifo_empty)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       630
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T32,T33,T63
0	0	1	0	Not Covered
0	1	0	0	Covered	T20,T4,T5
1	0	0	0	Covered	T27,T28,T29

 LINE       674
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T10,T11,T12
0	1	0	0	Unreachable
1	0	0	0	Covered	T10,T11,T12

 LINE       686
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T10,T11,T12
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T10,T11,T12
0	0	1	0	0	0	Covered	T10,T11,T12
0	1	0	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	0	Covered	T10,T11,T12

 LINE       727
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       729
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T14,T15

 LINE       743
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T14,T15,T23
1	Covered	T3,T14,T15

 LINE       970
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1100
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1342
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T64,T65
1	0	Covered	T1,T2,T3
1	1	Covered	T41,T64,T65

 LINE       1342
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T64,T65
1	0	Covered	T1,T2,T3
1	1	Covered	T41,T64,T65

 LINE       1371
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T10,T11,T12
0	0	1	0	0	Covered	T4,T5,T6
0	1	0	0	0	Covered	T10,T11,T12
1	0	0	0	0	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	64	64	100.00
Total Bits	4160	4160	100.00
Total Bits 0->1	2080	2080	100.00
Total Bits 1->0	2080	2080	100.00

Ports	64	64	100.00
Port Bits	4160	4160	100.00
Port Bits 0->1	2080	2080	100.00
Port Bits 1->0	2080	2080	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T15,T4,T5	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T15,T4,T5	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T15,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T13,T14	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T13,T15,T16	Yes	T13,T15,T16	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T28,T66,T67	Yes	T28,T66,T67	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T41,T64,T4	Yes	T41,T64,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T41,T64,T65	Yes	T41,T64,T65	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T41,T64,T4	Yes	T41,T64,T4	OUTPUT
keymgr_key_i.key[1:0][255:0]	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
keymgr_key_i.valid	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
app_i[0].last	Yes	Yes	T14,T15,T23	Yes	T14,T15,T23	INPUT
app_i[0].strb[7:0]	Yes	Yes	T14,T15,T27	Yes	T14,T15,T27	INPUT
app_i[0].data[63:0]	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
app_i[0].valid	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
app_i[1].last	Yes	Yes	T14,T23,T32	Yes	T14,T15,T23	INPUT
app_i[1].strb[7:0]	Yes	Yes	T14,T15,T27	Yes	T14,T15,T27	INPUT
app_i[1].data[63:0]	Yes	Yes	T14,T15,T23	Yes	T14,T15,T23	INPUT
app_i[1].valid	Yes	Yes	T14,T15,T4	Yes	T14,T15,T4	INPUT
app_i[2].last	Yes	Yes	T23,T32,T27	Yes	T15,T23,T32	INPUT
app_i[2].strb[7:0]	Yes	Yes	T15,T27,T30	Yes	T15,T27,T30	INPUT
app_i[2].data[63:0]	Yes	Yes	T15,T23,T32	Yes	T15,T23,T32	INPUT
app_i[2].valid	Yes	Yes	T15,T4,T23	Yes	T15,T4,T23	INPUT
app_o[0].error	Yes	Yes	T4,T5,T27	Yes	T4,T5,T27	OUTPUT
app_o[0].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[0].digest_share0[383:0]	Yes	Yes	T14,T15,T23	Yes	T14,T15,T23	OUTPUT
app_o[0].done	Yes	Yes	T14,T15,T23	Yes	T14,T15,T23	OUTPUT
app_o[0].ready	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	OUTPUT
app_o[1].error	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	OUTPUT
app_o[1].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[1].digest_share0[383:0]	Yes	Yes	T14,T15,T23	Yes	T14,T15,T23	OUTPUT
app_o[1].done	Yes	Yes	T14,T15,T23	Yes	T14,T15,T23	OUTPUT
app_o[1].ready	Yes	Yes	T14,T15,T23	Yes	T14,T15,T23	OUTPUT
app_o[2].error	Yes	Yes	T28,T29,T45	Yes	T28,T29,T45	OUTPUT
app_o[2].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[2].digest_share0[383:0]	Yes	Yes	T23,T27,T30	Yes	T23,T27,T30	OUTPUT
app_o[2].done	Yes	Yes	T15,T23,T32	Yes	T15,T23,T32	OUTPUT
app_o[2].ready	Yes	Yes	T15,T23,T32	Yes	T15,T23,T32	OUTPUT
entropy_o.edn_req[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_bus[31:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_fips[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_ack[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
intr_kmac_done_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fifo_empty_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_kmac_err_o	Yes	Yes	T20,T4,T5	Yes	T20,T4,T5	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	768	Covered	T1,T2,T3
KmacIdle	736	Covered	T1,T2,T3
KmacKeyBlock	743	Covered	T3,T14,T15
KmacMsgFeed	733	Covered	T1,T2,T3
KmacPrefix	730	Covered	T3,T14,T15
KmacTerminalError	785	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	777	Covered	T1,T2,T3
KmacDigest->KmacTerminalError	799	Covered	T43,T44
KmacIdle->KmacMsgFeed	733	Covered	T1,T2,T3
KmacIdle->KmacPrefix	730	Covered	T3,T14,T15
KmacIdle->KmacTerminalError	799	Covered	T10,T11,T12
KmacKeyBlock->KmacMsgFeed	752	Covered	T3,T14,T15
KmacKeyBlock->KmacTerminalError	799	Covered	T4,T5,T7
KmacMsgFeed->KmacDigest	768	Covered	T1,T2,T3
KmacMsgFeed->KmacIdle	765	Covered	T14,T15,T23
KmacMsgFeed->KmacTerminalError	799	Covered	T6,T9,T68
KmacPrefix->KmacKeyBlock	743	Covered	T3,T14,T15
KmacPrefix->KmacMsgFeed	743	Covered	T14,T15,T23
KmacPrefix->KmacTerminalError	799	Covered	T69,T8,T70

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		55	51	92.73
TERNARY	423	2	2	100.00
CASE	431	6	5	83.33
IF	485	3	3	100.00
IF	558	3	3	100.00
IF	607	2	2	100.00
CASE	640	6	4	66.67
IF	716	2	2	100.00
CASE	725	15	15	100.00
IF	798	2	2	100.00
TERNARY	1100	2	2	100.00
IF	1360	4	3	75.00
IF	1383	3	3	100.00
IF	1412	3	3	100.00
IF	1422	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T2,T3
CmdProcess	Covered	T1,T2,T3
CmdManualRun	Covered	T3,T14,T15
CmdDone	Covered	T1,T2,T3
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	if ((!rst_ni))
-2-:	560	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	607	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	640	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T20,T4,T5
errchecker_err.valid	Covered	T32,T33,T63
sha3_err.valid	Covered	T27,T28,T29
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	716	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	725	case (kmac_st)
-2-:	727	if ((kmac_cmd == CmdStart))
-3-:	729	if ((CShake == app_sha3_mode))
-4-:	742	if (sha3_block_processed)
-5-:	743	(app_kmac_en) ? 
-6-:	751	if (sha3_block_processed)
-7-:	760	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	766	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	776	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T3,T14,T15
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T3,T14,T15
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T14,T15,T23
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T3,T14,T15
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T3,T14,T15
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T3,T14,T15
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T14,T15,T23
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	798	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1100	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1360	if ((!rst_ni))
-2-:	1362	if (alert_recov_operation)
-3-:	1364	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T20,T21,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1383	if ((!rst_ni))
-2-:	1385	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1412	if ((!rst_ni))
-2-:	1414	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1422	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1298277	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	341393	0	0
EntrySizeRegSameToEntrySizePkg_A	1030	1030	0	0
ErrProcessedLatched_A	2147483647	572	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	80	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	80	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	80	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacFsmCheck_A	2147483647	80	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	80	0	0
FpvSecCmRoundCountCheck_A	2147483647	80	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	80	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	80	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	80	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1030	1030	0	0
NumEntriesRegSameToNumEntriesPkg_A	1030	1030	0	0
PrefixRegSameToPrefixPkg_A	1030	1030	0	0
SecretKeyDivideBy32_A	1030	1030	0	0
Sha3AbsorbedPulse_A	2147483647	351441	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1298277	0	0
T1	135261	983	0	0
T2	939753	786	0	0
T3	210024	1391	0	0
T13	328668	786	0	0
T14	488585	325	0	0
T15	169062	1043	0	0
T16	219586	7511	0	0
T17	16603	28	0	0
T18	70573	457	0	0
T19	232987	1166	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	341393	0	0
T1	135261	298	0	0
T2	939753	240	0	0
T3	210024	198	0	0
T13	328668	238	0	0
T14	488585	65	0	0
T15	169062	170	0	0
T16	219586	2269	0	0
T17	16603	9	0	0
T18	70573	140	0	0
T19	232987	162	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	572	0	0
T4	3317	0	0	0
T5	2853	0	0	0
T20	124123	20	0	0
T21	0	20	0	0
T22	0	8	0	0
T23	467564	0	0	0
T24	0	8	0	0
T61	371701	0	0	0
T62	127978	0	0	0
T65	1738	0	0	0
T71	0	3	0	0
T72	0	9	0	0
T73	0	2	0	0
T74	0	9	0	0
T75	0	14	0	0
T76	0	5	0	0
T77	122646	0	0	0
T78	16578	0	0	0
T79	123561	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T10	164673	10	0	0
T11	0	10	0	0
T12	0	20	0	0
T24	31854	0	0	0
T71	19532	0	0	0
T80	0	20	0	0
T81	0	20	0	0
T82	6082	0	0	0
T83	617098	0	0	0
T84	6562	0	0	0
T85	410237	0	0	0
T86	6949	0	0	0
T87	6235	0	0	0
T88	190889	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	351441	0	0
T1	135261	310	0	0
T2	939753	246	0	0
T3	210024	199	0	0
T13	328668	246	0	0
T14	488585	65	0	0
T15	169062	173	0	0
T16	219586	2337	0	0
T17	16603	9	0	0
T18	70573	142	0	0
T19	232987	162	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	135261	135252	0	0
T2	939753	939685	0	0
T3	210024	210018	0	0
T13	328668	328662	0	0
T14	488585	488487	0	0
T15	169062	169039	0	0
T16	219586	219585	0	0
T17	16603	16538	0	0
T18	70573	70493	0	0
T19	232987	232981	0	0