Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.80	96.15	91.89	100.00	100.00	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	678734	0	0
entropy_period_rd_A	2147483647	2299	0	0
intr_enable_rd_A	2147483647	3023	0	0
prefix_0_rd_A	2147483647	2220	0	0
prefix_10_rd_A	2147483647	2159	0	0
prefix_1_rd_A	2147483647	2339	0	0
prefix_2_rd_A	2147483647	2282	0	0
prefix_3_rd_A	2147483647	2219	0	0
prefix_4_rd_A	2147483647	2173	0	0
prefix_5_rd_A	2147483647	2327	0	0
prefix_6_rd_A	2147483647	2184	0	0
prefix_7_rd_A	2147483647	2238	0	0
prefix_8_rd_A	2147483647	2324	0	0
prefix_9_rd_A	2147483647	2207	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	678734	0	0
T28	277343	39622	0	0
T31	703763	0	0	0
T66	0	51021	0	0
T67	0	18666	0	0
T103	886257	0	0	0
T114	0	46901	0	0
T115	0	24745	0	0
T116	0	31725	0	0
T117	0	16956	0	0
T118	0	113606	0	0
T119	0	8538	0	0
T120	0	155547	0	0
T121	155317	0	0	0
T122	69213	0	0	0
T123	172689	0	0	0
T124	462745	0	0	0
T125	134147	0	0	0
T126	642269	0	0	0
T127	140082	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2299	0	0
T45	127359	0	0	0
T66	549887	159	0	0
T67	0	24	0	0
T73	15789	0	0	0
T92	0	28	0	0
T93	0	34	0	0
T108	0	118	0	0
T110	0	70	0	0
T136	233271	0	0	0
T137	0	41	0	0
T138	0	8	0	0
T139	0	18	0	0
T140	0	15	0	0
T141	651223	0	0	0
T142	6463	0	0	0
T143	453811	0	0	0
T144	168464	0	0	0
T145	129917	0	0	0
T146	1284	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3023	0	0
T45	127359	0	0	0
T66	549887	173	0	0
T67	0	34	0	0
T73	15789	0	0	0
T92	0	38	0	0
T93	0	23	0	0
T108	0	136	0	0
T110	0	79	0	0
T113	0	15	0	0
T136	233271	0	0	0
T137	0	47	0	0
T138	0	20	0	0
T139	0	22	0	0
T141	651223	0	0	0
T142	6463	0	0	0
T143	453811	0	0	0
T144	168464	0	0	0
T145	129917	0	0	0
T146	1284	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2220	0	0
T45	127359	0	0	0
T66	549887	135	0	0
T67	0	25	0	0
T73	15789	0	0	0
T92	0	34	0	0
T93	0	6	0	0
T108	0	86	0	0
T110	0	39	0	0
T136	233271	0	0	0
T137	0	44	0	0
T138	0	11	0	0
T139	0	23	0	0
T140	0	3	0	0
T141	651223	0	0	0
T142	6463	0	0	0
T143	453811	0	0	0
T144	168464	0	0	0
T145	129917	0	0	0
T146	1284	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2159	0	0
T45	127359	0	0	0
T66	549887	88	0	0
T67	0	35	0	0
T73	15789	0	0	0
T92	0	28	0	0
T93	0	16	0	0
T108	0	81	0	0
T110	0	59	0	0
T136	233271	0	0	0
T137	0	22	0	0
T138	0	36	0	0
T139	0	10	0	0
T140	0	11	0	0
T141	651223	0	0	0
T142	6463	0	0	0
T143	453811	0	0	0
T144	168464	0	0	0
T145	129917	0	0	0
T146	1284	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2339	0	0
T45	127359	0	0	0
T66	549887	195	0	0
T67	0	36	0	0
T73	15789	0	0	0
T92	0	22	0	0
T93	0	18	0	0
T108	0	68	0	0
T110	0	29	0	0
T136	233271	0	0	0
T137	0	63	0	0
T138	0	35	0	0
T139	0	26	0	0
T140	0	11	0	0
T141	651223	0	0	0
T142	6463	0	0	0
T143	453811	0	0	0
T144	168464	0	0	0
T145	129917	0	0	0
T146	1284	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2282	0	0
T45	127359	0	0	0
T66	549887	151	0	0
T67	0	22	0	0
T73	15789	0	0	0
T92	0	26	0	0
T93	0	17	0	0
T108	0	70	0	0
T110	0	27	0	0
T136	233271	0	0	0
T137	0	46	0	0
T138	0	44	0	0
T139	0	11	0	0
T140	0	6	0	0
T141	651223	0	0	0
T142	6463	0	0	0
T143	453811	0	0	0
T144	168464	0	0	0
T145	129917	0	0	0
T146	1284	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2219	0	0
T45	127359	0	0	0
T66	549887	145	0	0
T67	0	21	0	0
T73	15789	0	0	0
T92	0	33	0	0
T93	0	3	0	0
T108	0	69	0	0
T110	0	49	0	0
T136	233271	0	0	0
T137	0	34	0	0
T138	0	30	0	0
T139	0	20	0	0
T140	0	7	0	0
T141	651223	0	0	0
T142	6463	0	0	0
T143	453811	0	0	0
T144	168464	0	0	0
T145	129917	0	0	0
T146	1284	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2173	0	0
T45	127359	0	0	0
T66	549887	182	0	0
T67	0	39	0	0
T73	15789	0	0	0
T92	0	29	0	0
T93	0	13	0	0
T108	0	78	0	0
T110	0	40	0	0
T136	233271	0	0	0
T137	0	39	0	0
T138	0	17	0	0
T139	0	19	0	0
T140	0	6	0	0
T141	651223	0	0	0
T142	6463	0	0	0
T143	453811	0	0	0
T144	168464	0	0	0
T145	129917	0	0	0
T146	1284	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2327	0	0
T45	127359	0	0	0
T66	549887	148	0	0
T67	0	27	0	0
T73	15789	0	0	0
T92	0	30	0	0
T93	0	17	0	0
T108	0	98	0	0
T110	0	30	0	0
T136	233271	0	0	0
T137	0	65	0	0
T138	0	10	0	0
T139	0	17	0	0
T140	0	9	0	0
T141	651223	0	0	0
T142	6463	0	0	0
T143	453811	0	0	0
T144	168464	0	0	0
T145	129917	0	0	0
T146	1284	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2184	0	0
T45	127359	0	0	0
T66	549887	139	0	0
T67	0	33	0	0
T73	15789	0	0	0
T92	0	28	0	0
T93	0	9	0	0
T108	0	91	0	0
T110	0	31	0	0
T136	233271	0	0	0
T137	0	27	0	0
T138	0	4	0	0
T139	0	27	0	0
T140	0	4	0	0
T141	651223	0	0	0
T142	6463	0	0	0
T143	453811	0	0	0
T144	168464	0	0	0
T145	129917	0	0	0
T146	1284	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2238	0	0
T45	127359	0	0	0
T66	549887	133	0	0
T67	0	35	0	0
T73	15789	0	0	0
T92	0	29	0	0
T93	0	34	0	0
T108	0	73	0	0
T110	0	42	0	0
T136	233271	0	0	0
T137	0	67	0	0
T138	0	29	0	0
T139	0	14	0	0
T140	0	14	0	0
T141	651223	0	0	0
T142	6463	0	0	0
T143	453811	0	0	0
T144	168464	0	0	0
T145	129917	0	0	0
T146	1284	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2324	0	0
T45	127359	0	0	0
T66	549887	156	0	0
T67	0	15	0	0
T73	15789	0	0	0
T92	0	24	0	0
T93	0	5	0	0
T108	0	73	0	0
T110	0	36	0	0
T136	233271	0	0	0
T137	0	42	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	0	11	0	0
T141	651223	0	0	0
T142	6463	0	0	0
T143	453811	0	0	0
T144	168464	0	0	0
T145	129917	0	0	0
T146	1284	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2207	0	0
T45	127359	0	0	0
T66	549887	149	0	0
T67	0	15	0	0
T73	15789	0	0	0
T92	0	26	0	0
T93	0	14	0	0
T108	0	58	0	0
T110	0	50	0	0
T136	233271	0	0	0
T137	0	52	0	0
T138	0	41	0	0
T139	0	15	0	0
T140	0	8	0	0
T141	651223	0	0	0
T142	6463	0	0	0
T143	453811	0	0	0
T144	168464	0	0	0
T145	129917	0	0	0
T146	1284	0	0	0