Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	517810	0	0
entropy_period_rd_A	2147483647	1612	0	0
intr_enable_rd_A	2147483647	2021	0	0
prefix_0_rd_A	2147483647	1383	0	0
prefix_10_rd_A	2147483647	1228	0	0
prefix_1_rd_A	2147483647	1424	0	0
prefix_2_rd_A	2147483647	1332	0	0
prefix_3_rd_A	2147483647	1420	0	0
prefix_4_rd_A	2147483647	1382	0	0
prefix_5_rd_A	2147483647	1320	0	0
prefix_6_rd_A	2147483647	1380	0	0
prefix_7_rd_A	2147483647	1349	0	0
prefix_8_rd_A	2147483647	1301	0	0
prefix_9_rd_A	2147483647	1325	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	517810	0	0
T43	396352	56463	0	0
T48	0	25104	0	0
T49	0	33562	0	0
T114	0	87507	0	0
T115	0	7296	0	0
T116	0	83638	0	0
T117	0	139121	0	0
T118	0	26594	0	0
T119	0	54210	0	0
T120	0	192	0	0
T121	116673	0	0	0
T122	314523	0	0	0
T123	188597	0	0	0
T124	6491	0	0	0
T125	195281	0	0	0
T126	180780	0	0	0
T127	134558	0	0	0
T128	1088	0	0	0
T129	188107	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1612	0	0
T62	162999	0	0	0
T92	0	14	0	0
T99	0	16	0	0
T115	778021	40	0	0
T118	0	64	0	0
T119	0	135	0	0
T142	0	13	0	0
T143	0	1	0	0
T144	0	23	0	0
T145	0	18	0	0
T146	0	8	0	0
T147	174627	0	0	0
T148	657365	0	0	0
T149	358829	0	0	0
T150	105024	0	0	0
T151	422574	0	0	0
T152	33121	0	0	0
T153	117378	0	0	0
T154	549992	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2021	0	0
T62	162999	0	0	0
T99	0	19	0	0
T113	0	24	0	0
T115	778021	28	0	0
T118	0	19	0	0
T119	0	83	0	0
T142	0	15	0	0
T143	0	34	0	0
T144	0	11	0	0
T147	174627	0	0	0
T148	657365	0	0	0
T149	358829	0	0	0
T150	105024	0	0	0
T151	422574	0	0	0
T152	33121	0	0	0
T153	117378	0	0	0
T154	549992	0	0	0
T155	0	6	0	0
T156	0	22	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1383	0	0
T62	162999	0	0	0
T92	0	7	0	0
T99	0	13	0	0
T115	778021	54	0	0
T118	0	79	0	0
T119	0	163	0	0
T142	0	7	0	0
T143	0	49	0	0
T144	0	39	0	0
T145	0	14	0	0
T146	0	12	0	0
T147	174627	0	0	0
T148	657365	0	0	0
T149	358829	0	0	0
T150	105024	0	0	0
T151	422574	0	0	0
T152	33121	0	0	0
T153	117378	0	0	0
T154	549992	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1228	0	0
T62	162999	0	0	0
T92	0	19	0	0
T99	0	30	0	0
T115	778021	25	0	0
T118	0	48	0	0
T119	0	108	0	0
T142	0	14	0	0
T143	0	27	0	0
T144	0	27	0	0
T145	0	5	0	0
T146	0	3	0	0
T147	174627	0	0	0
T148	657365	0	0	0
T149	358829	0	0	0
T150	105024	0	0	0
T151	422574	0	0	0
T152	33121	0	0	0
T153	117378	0	0	0
T154	549992	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1424	0	0
T62	162999	0	0	0
T92	0	5	0	0
T99	0	21	0	0
T115	778021	35	0	0
T118	0	79	0	0
T119	0	204	0	0
T142	0	15	0	0
T143	0	45	0	0
T144	0	22	0	0
T145	0	12	0	0
T147	174627	0	0	0
T148	657365	0	0	0
T149	358829	0	0	0
T150	105024	0	0	0
T151	422574	0	0	0
T152	33121	0	0	0
T153	117378	0	0	0
T154	549992	0	0	0
T157	0	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1332	0	0
T62	162999	0	0	0
T92	0	13	0	0
T99	0	12	0	0
T115	778021	30	0	0
T118	0	65	0	0
T119	0	107	0	0
T142	0	26	0	0
T143	0	54	0	0
T144	0	43	0	0
T145	0	7	0	0
T146	0	6	0	0
T147	174627	0	0	0
T148	657365	0	0	0
T149	358829	0	0	0
T150	105024	0	0	0
T151	422574	0	0	0
T152	33121	0	0	0
T153	117378	0	0	0
T154	549992	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1420	0	0
T62	162999	0	0	0
T92	0	20	0	0
T99	0	22	0	0
T115	778021	36	0	0
T118	0	94	0	0
T119	0	162	0	0
T142	0	19	0	0
T143	0	46	0	0
T144	0	17	0	0
T145	0	17	0	0
T146	0	6	0	0
T147	174627	0	0	0
T148	657365	0	0	0
T149	358829	0	0	0
T150	105024	0	0	0
T151	422574	0	0	0
T152	33121	0	0	0
T153	117378	0	0	0
T154	549992	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1382	0	0
T62	162999	0	0	0
T92	0	13	0	0
T99	0	22	0	0
T115	778021	21	0	0
T118	0	44	0	0
T119	0	153	0	0
T142	0	20	0	0
T143	0	51	0	0
T144	0	5	0	0
T145	0	10	0	0
T146	0	3	0	0
T147	174627	0	0	0
T148	657365	0	0	0
T149	358829	0	0	0
T150	105024	0	0	0
T151	422574	0	0	0
T152	33121	0	0	0
T153	117378	0	0	0
T154	549992	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1320	0	0
T62	162999	0	0	0
T90	0	62	0	0
T99	0	20	0	0
T115	778021	17	0	0
T118	0	65	0	0
T119	0	119	0	0
T142	0	20	0	0
T143	0	71	0	0
T144	0	1	0	0
T145	0	4	0	0
T146	0	2	0	0
T147	174627	0	0	0
T148	657365	0	0	0
T149	358829	0	0	0
T150	105024	0	0	0
T151	422574	0	0	0
T152	33121	0	0	0
T153	117378	0	0	0
T154	549992	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1380	0	0
T62	162999	0	0	0
T92	0	11	0	0
T99	0	18	0	0
T115	778021	37	0	0
T118	0	76	0	0
T119	0	170	0	0
T142	0	28	0	0
T143	0	33	0	0
T144	0	8	0	0
T145	0	12	0	0
T146	0	2	0	0
T147	174627	0	0	0
T148	657365	0	0	0
T149	358829	0	0	0
T150	105024	0	0	0
T151	422574	0	0	0
T152	33121	0	0	0
T153	117378	0	0	0
T154	549992	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1349	0	0
T62	162999	0	0	0
T99	0	15	0	0
T115	778021	42	0	0
T118	0	87	0	0
T119	0	124	0	0
T142	0	12	0	0
T143	0	16	0	0
T144	0	30	0	0
T145	0	15	0	0
T146	0	12	0	0
T147	174627	0	0	0
T148	657365	0	0	0
T149	358829	0	0	0
T150	105024	0	0	0
T151	422574	0	0	0
T152	33121	0	0	0
T153	117378	0	0	0
T154	549992	0	0	0
T157	0	6	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1301	0	0
T62	162999	0	0	0
T92	0	22	0	0
T99	0	19	0	0
T115	778021	18	0	0
T118	0	67	0	0
T119	0	78	0	0
T142	0	21	0	0
T143	0	34	0	0
T144	0	16	0	0
T145	0	8	0	0
T146	0	7	0	0
T147	174627	0	0	0
T148	657365	0	0	0
T149	358829	0	0	0
T150	105024	0	0	0
T151	422574	0	0	0
T152	33121	0	0	0
T153	117378	0	0	0
T154	549992	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1325	0	0
T62	162999	0	0	0
T99	0	16	0	0
T115	778021	28	0	0
T118	0	100	0	0
T119	0	130	0	0
T142	0	9	0	0
T143	0	46	0	0
T144	0	11	0	0
T145	0	8	0	0
T146	0	14	0	0
T147	174627	0	0	0
T148	657365	0	0	0
T149	358829	0	0	0
T150	105024	0	0	0
T151	422574	0	0	0
T152	33121	0	0	0
T153	117378	0	0	0
T154	549992	0	0	0
T157	0	1	0	0