Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.19	96.27	93.33	63.67	100.00	93.85	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	97.24	96.27	93.33	100.00	100.00	93.85	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.24	96.27	93.33	100.00	100.00	93.85	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.09	96.18	92.38	100.00	88.64	94.52	98.84

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
intr_fifo_empty	86.94	90.00	77.78			80.00	100.00
intr_kmac_done	93.75	100.00	75.00			100.00	100.00
intr_kmac_err	93.75	100.00	75.00			100.00	100.00
kmac_csr_assert	100.00						100.00
sha3pad_assert_cov_if	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_app_intf	94.18	94.07	89.80		94.12	92.94	100.00
u_errchk	95.99	97.14	96.67		90.00	96.15	100.00
u_kmac_core	93.72	98.75	92.86	100.00	87.50	92.31	90.91
u_msgfifo	97.55	100.00	94.00		100.00	93.75	100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_reg	98.86	99.21	96.48	100.00		98.63	100.00
u_sha3	92.16	91.91	88.51	100.00	80.56	92.00	100.00
u_sha3_done_sender	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00
u_staterd	89.69	89.64	80.83			88.30	100.00
u_tlul_adapter_msgfifo	79.67	86.78	73.83			76.83	81.25

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		161	155	96.27
ALWAYS	343	0	0
ALWAYS	343	2	2	100.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	9	9	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	485	6	6	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	534	0	0
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
ALWAYS	558	5	5	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	633	1	1	100.00
CONT_ASSIGN	641	1	1	100.00
CONT_ASSIGN	646	1	1	100.00
ALWAYS	649	5	5	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	683	1	1	100.00
ALWAYS	686	7	5	71.43
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	727	1	0	0.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
ALWAYS	764	3	3	100.00
ALWAYS	768	28	28	100.00
CONT_ASSIGN	918	1	1	100.00
CONT_ASSIGN	921	1	1	100.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	1022	1	1	100.00
CONT_ASSIGN	1027	1	1	100.00
CONT_ASSIGN	1028	1	1	100.00
CONT_ASSIGN	1030	1	1	100.00
CONT_ASSIGN	1033	0	0
ALWAYS	1151	0	0
ALWAYS	1151	2	2	100.00
CONT_ASSIGN	1304	1	0	0.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
CONT_ASSIGN	1324	1	1	100.00
CONT_ASSIGN	1325	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1329	1	1	100.00
CONT_ASSIGN	1338	1	1	100.00
CONT_ASSIGN	1380	1	1	100.00
CONT_ASSIGN	1394	1	1	100.00
CONT_ASSIGN	1401	1	1	100.00
CONT_ASSIGN	1406	1	1	100.00
ALWAYS	1412	6	5	83.33
CONT_ASSIGN	1421	1	1	100.00
CONT_ASSIGN	1423	1	1	100.00
ALWAYS	1435	4	4	100.00
CONT_ASSIGN	1441	1	1	100.00
ALWAYS	1464	4	4	100.00
ALWAYS	1474	3	3	100.00
CONT_ASSIGN	1485	1	1	100.00
CONT_ASSIGN	1489	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	1	1
344	1	1
349	0	1
418	1	1
419	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
431	1	1
433	1	1
437	1	1
441	1	1
445	1	1
461	1	1
462	1	1
463	1	1
466	1	1
470	1	1
471	1	1
475	1	1
478	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
			MISSING_ELSE
510	1	1
515	1	1
522	1	1
525	1	1
526	1	1
527	1	1
529	1	1
530	1	1
532	1	1
534		unreachable
536	1	1
540	1	1
542	1	1
543	1	1
546	1	1
547	1	1
550	1	1
558	1	1
559	1	1
560	1	1
561	1	1
563	1	1
568	1	1
575	1	1
576	1	1
577	1	1
585	1	1
627	1	1
633	1	1
641	1	1
646	1	1
649	1	1
650	1	1
651	1	1
653	1	1
654	1	1
678	1	1
683	1	1
686	1	1
688	1	1
693	1	1
697	1	1
701	1	1
705	0	1
709	0	1
722	1	1
727	0	1
734	1	1
744	1	1
764	3	3
768	1	1
770	1	1
771	1	1
773	1	1
775	1	1
777	1	1
778	1	1
781	1	1
784	1	1
790	1	1
791	1	1
793	1	1
798	1	1
799	1	1
800	1	1
802	1	1
808	1	1
813	1	1
814	1	1
816	1	1
818	1	1
824	1	1
825	1	1
827	1	1
833	1	1
834	1	1
846	1	1
847	1	1
			MISSING_ELSE
918	1	1
921	1	1
990	1	1
992	1	1
1022	1	1
1027	1	1
1028	1	1
1030	1	1
1033		unreachable
1151	1	1
1152	1	1
1304	0	1
1305	1	1
1306	1	1
1316	1	1
1317	1	1
1323	1	1
1324	1	1
1325	1	1
1326	1	1
1329	1	1
1338	1	1
1380	1	1
1394	1	1
1401	1	1
1406	1	1
1412	1	1
1413	1	1
1414	1	1
1415	0	1
1416	1	1
1417	1	1
			MISSING_ELSE
1421	1	1
1423	1	1
1435	1	1
1436	1	1
1437	1	1
1438	1	1
			MISSING_ELSE
1441	1	1
1464	1	1
1465	1	1
1466	1	1
1468	1	1
			MISSING_ELSE
1474	1	1
1475	1	1
1478	1	1
1485	1	1
1489	1	1
1491	6	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	90	84	93.33
Logical	90	84	93.33
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T13,T14

 LINE       536
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T13,T14

 LINE       540
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       547
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T1,T3,T4

 LINE       560
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T4
1	-	Covered	T1,T2,T3

 LINE       568
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       627
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       633
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T29,T30

 LINE       633
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       633
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       641
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T13,T14

 LINE       641
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       641
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       641
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       646
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T28,T42,T43
1	Covered	T1,T2,T3

 LINE       678
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T16,T31,T45
0	0	1	0	Not Covered
0	1	0	0	Covered	T20,T16,T21
1	0	0	0	Covered	T26,T27,T28

 LINE       722
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T5,T11,T12
0	1	0	0	Unreachable
1	0	0	0	Covered	T5,T11,T12

 LINE       734
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T5,T11,T12
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T5,T11,T12
0	0	1	0	0	0	Covered	T5,T11,T12
0	1	0	0	0	0	Covered	T5,T11,T12
1	0	0	0	0	0	Covered	T5,T11,T12

 LINE       775
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       777
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T4,T13

 LINE       791
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T13,T14
1	Covered	T1,T4,T13

 LINE       1022
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       1152
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1394
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T46,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T46,T47

 LINE       1394
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T46,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T46,T47

 LINE       1423
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T5,T11,T12
0	0	1	0	0	Covered	T5,T6,T7
0	1	0	0	0	Covered	T5,T11,T12
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	64	90.14
Total Bits	6534	4160	63.67
Total Bits 0->1	3267	2080	63.67
Total Bits 1->0	3267	2080	63.67

Ports	71	64	90.14
Port Bits	6534	4160	63.67
Port Bits 0->1	3267	2080	63.67
Port Bits 1->0	3267	2080	63.67

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T26,T6	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T5,T26,T6	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T5,T26,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T13	Yes	T1,T2,T13	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T43,T48,T49	Yes	T43,T48,T49	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	OUTPUT
keymgr_key_i.key[0][3:0]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][4]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][12:5]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][13]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][18:14]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][19]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][23:20]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][25:24]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][63:26]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][64]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][74:65]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][75]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][105:76]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][106]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][149:107]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][150]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][176:151]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][177]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][200:178]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][202:201]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][243:203]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][244]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][255:245]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][3:0]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][4]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][17:5]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][18]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][20:19]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][21]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][44:22]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][45]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][50:46]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][51]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][71:52]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][72]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][73]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][74]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][76:75]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][77]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][89:78]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][90]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][148:91]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][149]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][156:150]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][157]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][169:158]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][170]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][175:171]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][176]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][209:177]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][210]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][213:211]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][214]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][215]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][229:216]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][230]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][253:231]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][254]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][255]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.valid	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
app_i[0].last	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[0].strb[7:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[0].data[63:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[0].valid	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[1].last	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[1].strb[7:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[1].data[63:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[1].valid	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[2].last	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[2].strb[7:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[2].data[63:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[2].valid	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_o[0].error	Yes	Yes	T5,T26,T27	Yes	T5,T26,T27	OUTPUT
app_o[0].digest_share1[383:0]	No	No		No		OUTPUT
app_o[0].digest_share0[383:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[0].done	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[0].ready	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[1].error	Yes	Yes	T26,T27,T7	Yes	T26,T27,T7	OUTPUT
app_o[1].digest_share1[383:0]	No	No		No		OUTPUT
app_o[1].digest_share0[383:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[1].done	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[1].ready	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[2].error	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
app_o[2].digest_share1[383:0]	No	No		No		OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[2].done	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[2].ready	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
entropy_o.edn_req	No	No		No		OUTPUT
entropy_i.edn_bus[31:0]	No	No		No		INPUT
entropy_i.edn_fips	No	No		No		INPUT
entropy_i.edn_ack	No	No		No		INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T7,T8,T35	Yes	T7,T8,T35	INPUT
intr_kmac_done_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
intr_fifo_empty_o	Yes	Yes	T28,T42,T43	Yes	T28,T42,T43	OUTPUT
intr_kmac_err_o	Yes	Yes	T20,T16,T21	Yes	T20,T16,T21	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	816	Covered	T1,T3,T4
KmacIdle	784	Covered	T1,T2,T3
KmacKeyBlock	791	Covered	T1,T4,T13
KmacMsgFeed	781	Covered	T1,T3,T4
KmacPrefix	778	Covered	T1,T4,T13
KmacTerminalError	833	Covered	T5,T6,T7

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	825	Covered	T1,T3,T4
KmacDigest->KmacTerminalError	847	Covered	T50
KmacIdle->KmacMsgFeed	781	Covered	T1,T3,T4
KmacIdle->KmacPrefix	778	Covered	T1,T4,T13
KmacIdle->KmacTerminalError	847	Covered	T5,T11,T12
KmacKeyBlock->KmacMsgFeed	800	Covered	T1,T4,T13
KmacKeyBlock->KmacTerminalError	847	Covered	T6,T51
KmacMsgFeed->KmacDigest	816	Covered	T1,T3,T4
KmacMsgFeed->KmacIdle	813	Covered	T1,T13,T14
KmacMsgFeed->KmacTerminalError	847	Covered	T7,T39,T52
KmacPrefix->KmacKeyBlock	791	Covered	T1,T4,T13
KmacPrefix->KmacMsgFeed	791	Covered	T1,T13,T14
KmacPrefix->KmacTerminalError	847	Covered	T8,T35,T9

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		65	61	93.85
TERNARY	423	2	2	100.00
TERNARY	633	4	4	100.00
TERNARY	641	4	4	100.00
TERNARY	646	2	2	100.00
CASE	431	6	5	83.33
IF	485	3	3	100.00
IF	558	3	3	100.00
IF	649	2	2	100.00
CASE	688	6	4	66.67
IF	764	2	2	100.00
CASE	773	15	15	100.00
IF	846	2	2	100.00
TERNARY	1152	2	2	100.00
IF	1412	4	3	75.00
IF	1435	3	3	100.00
IF	1464	3	3	100.00
IF	1474	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	633	(msgfifo_full) ? 
-2-:	633	(msgfifo_empty_negedge) ? 
-3-:	633	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T29,T30
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	641	(app_active) ? 
-2-:	641	((sha3_fsm != StAbsorb)) ? 
-3-:	641	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T13,T14
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	646	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T28,T42,T43

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T3,T4
CmdProcess	Covered	T1,T3,T4
CmdManualRun	Covered	T1,T4,T13
CmdDone	Covered	T1,T3,T4
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	558	if ((!rst_ni))
-2-:	560	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	649	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	688	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T20,T16,T21
errchecker_err.valid	Covered	T16,T31,T45
sha3_err.valid	Covered	T26,T27,T28
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	764	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	773	case (kmac_st)
-2-:	775	if ((kmac_cmd == CmdStart))
-3-:	777	if ((CShake == app_sha3_mode))
-4-:	790	if (sha3_block_processed)
-5-:	791	(app_kmac_en) ? 
-6-:	799	if (sha3_block_processed)
-7-:	808	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	814	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	824	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T1,T4,T13
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T3,T4
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T1,T4,T13
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T1,T13,T14
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T1,T4,T13
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T1,T4,T13
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T1,T4,T13
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T1,T13,T14
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T3,T4
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
default	-	-	-	-	-	-	-	-	Covered	T5,T11,T12

	LineNo.	Expression
-1-:	846	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1152	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1412	if ((!rst_ni))
-2-:	1414	if (alert_recov_operation)
-3-:	1416	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T20,T21,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1435	if ((!rst_ni))
-2-:	1437	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1464	if ((!rst_ni))
-2-:	1466	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1474	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1280976	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	337974	0	0
EntrySizeRegSameToEntrySizePkg_A	1029	1029	0	0
ErrProcessedLatched_A	2147483647	552	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	80	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	80	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	80	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacFsmCheck_A	2147483647	80	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	80	0	0
FpvSecCmRoundCountCheck_A	2147483647	80	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	80	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	80	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	80	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1029	1029	0	0
NumEntriesRegSameToNumEntriesPkg_A	1029	1029	0	0
PrefixRegSameToPrefixPkg_A	1029	1029	0	0
SecretKeyDivideBy32_A	1029	1029	0	0
Sha3AbsorbedPulse_A	2147483647	348029	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1280976	0	0
T1	129585	1023	0	0
T2	1194	0	0	0
T3	189230	1246	0	0
T4	781139	845	0	0
T13	328928	272	0	0
T14	141051	904	0	0
T15	97985	52	0	0
T16	285064	908	0	0
T17	16223	38	0	0
T18	0	7453	0	0
T19	0	1207	0	0
T20	46988	0	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	337974	0	0
T1	129585	167	0	0
T2	1194	0	0	0
T3	189230	377	0	0
T4	781139	113	0	0
T13	328928	44	0	0
T14	141051	173	0	0
T15	97985	8	0	0
T16	285064	122	0	0
T17	16223	6	0	0
T18	0	2257	0	0
T20	46988	8	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	552	0	0
T15	97985	0	0	0
T16	285064	0	0	0
T17	16223	0	0	0
T18	221634	0	0	0
T19	807161	0	0	0
T20	46988	8	0	0
T21	0	18	0	0
T22	0	18	0	0
T40	138680	0	0	0
T46	1578	0	0	0
T53	0	7	0	0
T54	0	18	0	0
T55	0	15	0	0
T56	0	19	0	0
T57	0	12	0	0
T58	0	15	0	0
T59	0	16	0	0
T60	6500	0	0	0
T61	236500	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	348029	0	0
T1	129585	167	0	0
T2	1194	0	0	0
T3	189230	390	0	0
T4	781139	113	0	0
T13	328928	44	0	0
T14	141051	173	0	0
T15	97985	8	0	0
T16	285064	119	0	0
T17	16223	6	0	0
T18	0	2337	0	0
T19	0	374	0	0
T20	46988	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		161	155	96.27
ALWAYS	343	0	0
ALWAYS	343	2	2	100.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	9	9	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	485	6	6	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	534	0	0
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	542	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
ALWAYS	558	5	5	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	633	1	1	100.00
CONT_ASSIGN	641	1	1	100.00
CONT_ASSIGN	646	1	1	100.00
ALWAYS	649	5	5	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	683	1	1	100.00
ALWAYS	686	7	5	71.43
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	727	1	0	0.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
ALWAYS	764	3	3	100.00
ALWAYS	768	28	28	100.00
CONT_ASSIGN	918	1	1	100.00
CONT_ASSIGN	921	1	1	100.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	1022	1	1	100.00
CONT_ASSIGN	1027	1	1	100.00
CONT_ASSIGN	1028	1	1	100.00
CONT_ASSIGN	1030	1	1	100.00
CONT_ASSIGN	1033	0	0
ALWAYS	1151	0	0
ALWAYS	1151	2	2	100.00
CONT_ASSIGN	1304	1	0	0.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
CONT_ASSIGN	1324	1	1	100.00
CONT_ASSIGN	1325	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1329	1	1	100.00
CONT_ASSIGN	1338	1	1	100.00
CONT_ASSIGN	1380	1	1	100.00
CONT_ASSIGN	1394	1	1	100.00
CONT_ASSIGN	1401	1	1	100.00
CONT_ASSIGN	1406	1	1	100.00
ALWAYS	1412	6	5	83.33
CONT_ASSIGN	1421	1	1	100.00
CONT_ASSIGN	1423	1	1	100.00
ALWAYS	1435	4	4	100.00
CONT_ASSIGN	1441	1	1	100.00
ALWAYS	1464	4	4	100.00
ALWAYS	1474	3	3	100.00
CONT_ASSIGN	1485	1	1	100.00
CONT_ASSIGN	1489	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	1	1
344	1	1
349	0	1
418	1	1
419	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
431	1	1
433	1	1
437	1	1
441	1	1
445	1	1
461	1	1
462	1	1
463	1	1
466	1	1
470	1	1
471	1	1
475	1	1
478	1	1
485	1	1
486	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
			MISSING_ELSE
510	1	1
515	1	1
522	1	1
525	1	1
526	1	1
527	1	1
529	1	1
530	1	1
532	1	1
534		unreachable
536	1	1
540	1	1
542	1	1
543	1	1
546	1	1
547	1	1
550	1	1
558	1	1
559	1	1
560	1	1
561	1	1
563	1	1
568	1	1
575	1	1
576	1	1
577	1	1
585	1	1
627	1	1
633	1	1
641	1	1
646	1	1
649	1	1
650	1	1
651	1	1
653	1	1
654	1	1
678	1	1
683	1	1
686	1	1
688	1	1
693	1	1
697	1	1
701	1	1
705	0	1
709	0	1
722	1	1
727	0	1
734	1	1
744	1	1
764	3	3
768	1	1
770	1	1
771	1	1
773	1	1
775	1	1
777	1	1
778	1	1
781	1	1
784	1	1
790	1	1
791	1	1
793	1	1
798	1	1
799	1	1
800	1	1
802	1	1
808	1	1
813	1	1
814	1	1
816	1	1
818	1	1
824	1	1
825	1	1
827	1	1
833	1	1
834	1	1
846	1	1
847	1	1
			MISSING_ELSE
918	1	1
921	1	1
990	1	1
992	1	1
1022	1	1
1027	1	1
1028	1	1
1030	1	1
1033		unreachable
1151	1	1
1152	1	1
1304	0	1
1305	1	1
1306	1	1
1316	1	1
1317	1	1
1323	1	1
1324	1	1
1325	1	1
1326	1	1
1329	1	1
1338	1	1
1380	1	1
1394	1	1
1401	1	1
1406	1	1
1412	1	1
1413	1	1
1414	1	1
1415	0	1
1416	1	1
1417	1	1
			MISSING_ELSE
1421	1	1
1423	1	1
1435	1	1
1436	1	1
1437	1	1
1438	1	1
			MISSING_ELSE
1441	1	1
1464	1	1
1465	1	1
1466	1	1
1468	1	1
			MISSING_ELSE
1474	1	1
1475	1	1
1478	1	1
1485	1	1
1489	1	1
1491	6	6

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	90	84	93.33
Logical	90	84	93.33
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T13,T14

 LINE       536
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T13,T14

 LINE       540
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       547
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T1,T3,T4

 LINE       560
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       560
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T4
1	-	Covered	T1,T2,T3

 LINE       568
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       627
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       633
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T29,T30

 LINE       633
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       633
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       641
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T13,T14

 LINE       641
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       641
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       641
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       646
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Covered	T28,T42,T43
1	Covered	T1,T2,T3

 LINE       678
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T16,T31,T45
0	0	1	0	Not Covered
0	1	0	0	Covered	T20,T16,T21
1	0	0	0	Covered	T26,T27,T28

 LINE       722
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T5,T11,T12
0	1	0	0	Unreachable
1	0	0	0	Covered	T5,T11,T12

 LINE       734
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T5,T11,T12
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Covered	T5,T11,T12
0	0	1	0	0	0	Covered	T5,T11,T12
0	1	0	0	0	0	Covered	T5,T11,T12
1	0	0	0	0	0	Covered	T5,T11,T12

 LINE       775
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       777
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T4,T13

 LINE       791
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T13,T14
1	Covered	T1,T4,T13

 LINE       1022
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       1152
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1394
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T46,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T46,T47

 LINE       1394
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T46,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T46,T47

 LINE       1423
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Covered	T5,T11,T12
0	0	1	0	0	Covered	T5,T6,T7
0	1	0	0	0	Covered	T5,T11,T12
1	0	0	0	0	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	64	64	100.00
Total Bits	4160	4160	100.00
Total Bits 0->1	2080	2080	100.00
Total Bits 1->0	2080	2080	100.00

Ports	64	64	100.00
Port Bits	4160	4160	100.00
Port Bits 0->1	2080	2080	100.00
Port Bits 1->0	2080	2080	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T26,T6	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T5,T26,T6	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T5,T26,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T13	Yes	T1,T2,T13	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T43,T48,T49	Yes	T43,T48,T49	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	OUTPUT
keymgr_key_i.key[0][3:0]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][4]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][12:5]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][13]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][18:14]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][19]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][23:20]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][25:24]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][63:26]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][64]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][74:65]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][75]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][105:76]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][106]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][149:107]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][150]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][176:151]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][177]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][200:178]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][202:201]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][243:203]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][244]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[0][255:245]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][3:0]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][4]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][17:5]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][18]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][20:19]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][21]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][44:22]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][45]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][50:46]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][51]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][71:52]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][72]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][73]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][74]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][76:75]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][77]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][89:78]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][90]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][148:91]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][149]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][156:150]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][157]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][169:158]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][170]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][175:171]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][176]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][209:177]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][210]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][213:211]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][214]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][215]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][229:216]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][230]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][253:231]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][254]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.key[1][255]	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
keymgr_key_i.valid	Yes	Yes	T1,T4,T13	Yes	T1,T4,T13	INPUT
app_i[0].last	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[0].strb[7:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[0].data[63:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[0].valid	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[1].last	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[1].strb[7:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[1].data[63:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[1].valid	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[2].last	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[2].strb[7:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[2].data[63:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_i[2].valid	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
app_o[0].error	Yes	Yes	T5,T26,T27	Yes	T5,T26,T27	OUTPUT
app_o[0].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[0].digest_share0[383:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[0].done	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[0].ready	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[1].error	Yes	Yes	T26,T27,T7	Yes	T26,T27,T7	OUTPUT
app_o[1].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[1].digest_share0[383:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[1].done	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[1].ready	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[2].error	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
app_o[2].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[2].digest_share0[383:0]	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[2].done	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
app_o[2].ready	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	OUTPUT
entropy_o.edn_req[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_bus[31:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_fips[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_ack[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
lc_escalate_en_i[3:0]	Yes	Yes	T7,T8,T35	Yes	T7,T8,T35	INPUT
intr_kmac_done_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
intr_fifo_empty_o	Yes	Yes	T28,T42,T43	Yes	T28,T42,T43	OUTPUT
intr_kmac_err_o	Yes	Yes	T20,T16,T21	Yes	T20,T16,T21	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	816	Covered	T1,T3,T4
KmacIdle	784	Covered	T1,T2,T3
KmacKeyBlock	791	Covered	T1,T4,T13
KmacMsgFeed	781	Covered	T1,T3,T4
KmacPrefix	778	Covered	T1,T4,T13
KmacTerminalError	833	Covered	T5,T6,T7

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	825	Covered	T1,T3,T4
KmacDigest->KmacTerminalError	847	Covered	T50
KmacIdle->KmacMsgFeed	781	Covered	T1,T3,T4
KmacIdle->KmacPrefix	778	Covered	T1,T4,T13
KmacIdle->KmacTerminalError	847	Covered	T5,T11,T12
KmacKeyBlock->KmacMsgFeed	800	Covered	T1,T4,T13
KmacKeyBlock->KmacTerminalError	847	Covered	T6,T51
KmacMsgFeed->KmacDigest	816	Covered	T1,T3,T4
KmacMsgFeed->KmacIdle	813	Covered	T1,T13,T14
KmacMsgFeed->KmacTerminalError	847	Covered	T7,T39,T52
KmacPrefix->KmacKeyBlock	791	Covered	T1,T4,T13
KmacPrefix->KmacMsgFeed	791	Covered	T1,T13,T14
KmacPrefix->KmacTerminalError	847	Covered	T8,T35,T9

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		65	61	93.85
TERNARY	423	2	2	100.00
TERNARY	633	4	4	100.00
TERNARY	641	4	4	100.00
TERNARY	646	2	2	100.00
CASE	431	6	5	83.33
IF	485	3	3	100.00
IF	558	3	3	100.00
IF	649	2	2	100.00
CASE	688	6	4	66.67
IF	764	2	2	100.00
CASE	773	15	15	100.00
IF	846	2	2	100.00
TERNARY	1152	2	2	100.00
IF	1412	4	3	75.00
IF	1435	3	3	100.00
IF	1464	3	3	100.00
IF	1474	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	633	(msgfifo_full) ? 
-2-:	633	(msgfifo_empty_negedge) ? 
-3-:	633	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T29,T30
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	641	(app_active) ? 
-2-:	641	((sha3_fsm != StAbsorb)) ? 
-3-:	641	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T13,T14
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	646	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T28,T42,T43

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Covered	T1,T3,T4
CmdProcess	Covered	T1,T3,T4
CmdManualRun	Covered	T1,T4,T13
CmdDone	Covered	T1,T3,T4
CmdNone	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	558	if ((!rst_ni))
-2-:	560	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	649	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	688	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Covered	T20,T16,T21
errchecker_err.valid	Covered	T16,T31,T45
sha3_err.valid	Covered	T26,T27,T28
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	764	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	773	case (kmac_st)
-2-:	775	if ((kmac_cmd == CmdStart))
-3-:	777	if ((CShake == app_sha3_mode))
-4-:	790	if (sha3_block_processed)
-5-:	791	(app_kmac_en) ? 
-6-:	799	if (sha3_block_processed)
-7-:	808	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	814	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	824	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Covered	T1,T4,T13
KmacIdle	1	0	-	-	-	-	-	-	Covered	T1,T3,T4
KmacIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
KmacPrefix	-	-	1	1	-	-	-	-	Covered	T1,T4,T13
KmacPrefix	-	-	1	0	-	-	-	-	Covered	T1,T13,T14
KmacPrefix	-	-	0	-	-	-	-	-	Covered	T1,T4,T13
KmacKeyBlock	-	-	-	-	1	-	-	-	Covered	T1,T4,T13
KmacKeyBlock	-	-	-	-	0	-	-	-	Covered	T1,T4,T13
KmacMsgFeed	-	-	-	-	-	1	-	-	Covered	T1,T13,T14
KmacMsgFeed	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
KmacMsgFeed	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
KmacDigest	-	-	-	-	-	-	-	1	Covered	T1,T3,T4
KmacDigest	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
KmacTerminalError	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
default	-	-	-	-	-	-	-	-	Covered	T5,T11,T12

	LineNo.	Expression
-1-:	846	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1152	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1412	if ((!rst_ni))
-2-:	1414	if (alert_recov_operation)
-3-:	1416	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T20,T21,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1435	if ((!rst_ni))
-2-:	1437	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1464	if ((!rst_ni))
-2-:	1466	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1474	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CmdSparse_M	2147483647	1280976	0	0
EnMaskingKnown_A	2147483647	2147483647	0	0
EntropyReadyLatched_A	2147483647	337974	0	0
EntrySizeRegSameToEntrySizePkg_A	1029	1029	0	0
ErrProcessedLatched_A	2147483647	552	0	0
FifoEmpty_A	2147483647	2147483647	0	0
FpvSecCmErrorCheckFsmCheck_A	2147483647	80	0	0
FpvSecCmKeccackFsmCheck_A	2147483647	80	0	0
FpvSecCmKeyIndexCountCheck_A	2147483647	80	0	0
FpvSecCmKmacAppFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacCoreFsmCheck_A	2147483647	80	0	0
FpvSecCmKmacFsmCheck_A	2147483647	80	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	80	0	0
FpvSecCmRoundCountCheck_A	2147483647	80	0	0
FpvSecCmSHA3FsmCheck_A	2147483647	80	0	0
FpvSecCmSHA3padFsmCheck_A	2147483647	80	0	0
FpvSecCmSentMsgCountCheck_A	2147483647	80	0	0
KmacCmd_A	2147483647	2147483647	0	0
KmacDone_A	2147483647	2147483647	0	0
KmacErr_A	2147483647	2147483647	0	0
KmacStKnown_A	2147483647	2147483647	0	0
NumAlerts2_A	1029	1029	0	0
NumEntriesRegSameToNumEntriesPkg_A	1029	1029	0	0
PrefixRegSameToPrefixPkg_A	1029	1029	0	0
SecretKeyDivideBy32_A	1029	1029	0	0
Sha3AbsorbedPulse_A	2147483647	348029	0	0
TlOAReadyKnown_A	2147483647	2147483647	0	0
TlODValidKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

CmdSparse_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1280976	0	0
T1	129585	1023	0	0
T2	1194	0	0	0
T3	189230	1246	0	0
T4	781139	845	0	0
T13	328928	272	0	0
T14	141051	904	0	0
T15	97985	52	0	0
T16	285064	908	0	0
T17	16223	38	0	0
T18	0	7453	0	0
T19	0	1207	0	0
T20	46988	0	0	0

EnMaskingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

EntropyReadyLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	337974	0	0
T1	129585	167	0	0
T2	1194	0	0	0
T3	189230	377	0	0
T4	781139	113	0	0
T13	328928	44	0	0
T14	141051	173	0	0
T15	97985	8	0	0
T16	285064	122	0	0
T17	16223	6	0	0
T18	0	2257	0	0
T20	46988	8	0	0

EntrySizeRegSameToEntrySizePkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

ErrProcessedLatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	552	0	0
T15	97985	0	0	0
T16	285064	0	0	0
T17	16223	0	0	0
T18	221634	0	0	0
T19	807161	0	0	0
T20	46988	8	0	0
T21	0	18	0	0
T22	0	18	0	0
T40	138680	0	0	0
T46	1578	0	0	0
T53	0	7	0	0
T54	0	18	0	0
T55	0	15	0	0
T56	0	19	0	0
T57	0	12	0	0
T58	0	15	0	0
T59	0	16	0	0
T60	6500	0	0	0
T61	236500	0	0	0

FifoEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

FpvSecCmErrorCheckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmKeccackFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmKeyIndexCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmKmacAppFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmKmacCoreFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmKmacFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmRoundCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmSHA3FsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmSHA3padFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

FpvSecCmSentMsgCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80	0	0
T5	314413	20	0	0
T11	0	20	0	0
T12	0	10	0	0
T53	28000	0	0	0
T54	78822	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	6174	0	0	0
T65	16945	0	0	0
T66	206250	0	0	0
T67	20944	0	0	0
T68	7415	0	0	0
T69	116022	0	0	0
T70	107052	0	0	0

KmacCmd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

KmacDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

KmacErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

KmacStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

NumAlerts2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

NumEntriesRegSameToNumEntriesPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

PrefixRegSameToPrefixPkg_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

SecretKeyDivideBy32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

Sha3AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	348029	0	0
T1	129585	167	0	0
T2	1194	0	0	0
T3	189230	390	0	0
T4	781139	113	0	0
T13	328928	44	0	0
T14	141051	173	0	0
T15	97985	8	0	0
T16	285064	119	0	0
T17	16223	6	0	0
T18	0	2337	0	0
T19	0	374	0	0
T20	46988	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	129585	129575	0	0
T2	1194	1127	0	0
T3	189230	189223	0	0
T4	781139	781132	0	0
T13	328928	328835	0	0
T14	141051	141042	0	0
T15	97985	97889	0	0
T16	285064	284997	0	0
T17	16223	16171	0	0
T20	46988	46896	0	0